Path Selection Based on Incremental Technique

Cremoux, Séverine; Azémard, Nadine; Auvergne, D.

doi:10.1007/978-1-4615-5651-0_21

Cited by 5 publications

(1 citation statement)

References 9 publications

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“…This delay profiling has been obtained from a previously developed path analyzer 15 of which accuracy has been demonstrated with respect to available industrial tools. The layout of the circuit has been obtained from an automatic layout generator 16 and the timing analysis performed on a post layout extraction of the circuit.…”

Section: Circuit Path Delay Profile Evolutionmentioning

confidence: 99%

Delay-bound determination for path constraint satisfaction

2000

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This paper addresses the problem of path constraint satisfaction from delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factor and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.

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Section: Circuit Path Delay Profile Evolutionmentioning

confidence: 99%

Delay-bound determination for path constraint satisfaction

2000

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Performance Metric Based Optimization Protocol

Michel

Verle

Maurine

et al. 2004

Lecture Notes in Computer Science

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Optimizing digital designs implies a selection of circuit implementation based on different cost criteria. Post-processing methods such as transistor sizing, buffer insertion or logic transformation can be used for optimizing critical paths to satisfy timing constraints. However most optimization tools are not able to select between the different optimization alternatives and have high CPU execution time.In this paper, we propose an optimization protocol based on metrics allowing to characterize a path and to select the best optimization alternative. We define a way to characterize the design space of any circuit implementation. Then we propose a constraint distribution method allowing constraint satisfaction at nearly minimum area. This quasi optimal tool is implemented in an optimization tool (POPS) and validated by comparing the area necessary to satisfy delay constraints applied to various benchmarks (ISCAS'85) to that resulting from an industrial tool.

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POPS: A tool for delay/power performance optimization

Azémard

Auvergne

2001

Journal of Systems Architecture

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Path Selection Based on Incremental Technique

Cited by 5 publications

References 9 publications

Delay-bound determination for path constraint satisfaction

Delay-bound determination for path constraint satisfaction

Performance Metric Based Optimization Protocol

POPS: A tool for delay/power performance optimization

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