Path clustering for adaptive test

Abstract

Adaptive test is one of the most efficient techniques that practically ensure high yield and reliability of designed chips. In this paper, a novel path-clustering method suitable for the adaptive test, in which test paths are altered according to the monitored process-parameters, is proposed. Considering the probability function of the die-to-die systematic process variation, the proposed method clusters path sets so that the total number of test-paths are minimized. For quantitative evaluation of different clusterings, figure of merit for clustering, which represents the expected number of test-paths at a particular test coverage, is also proposed. The proposed clustering is experimentally evaluated by applying to an industrial circuit. With our clustering, the average test paths in the adaptive test have been reduced to less than 50% compared with the ones of the conventional test.

Improved path clustering for adaptive path-delay testing

“…PREVIOUS WORK Uezono et al in [5] propose a Greedy algorithm for the clustering problem in Section II. The Greedy algorithm first generates M clusters of critical paths by defining C j = S j , then iteratively merges two clusters at a time until the total number of clusters is equal to k. In each iteration, the algorithm merges two clusters C i and C j with minimal distance (d i, j ) defined as…”

“…It differs from [2] in that the cost calculation is not defined by net "cuts", but rather by the number of nets in each cluster. 5 …”

“…Clearly, the efficiency of the adaptive testing -and hence the cost of test -is affected by the quality of the process condition clustering. 1 In this paper, we propose a new clustering algorithm that significantly improves efficiency of the adaptive test methodology, compared with a recent greedy approach of Uezono et al [5].…”

“…In this paper, we propose a new clustering heuristic to minimize the expected number of redundant test paths in adaptive path-delay testing. Our experimental results on randomly generated testcases show that the proposed clustering heuristic can reduce the expected number of test paths by up to 40% compared to the previous Greedy clustering algorithm of Uezono et al [5]. To address unique attributes of an industrial testcase obtained from the authors of [5], we integrate the dynamic-programming restricted-partitioning technique of [1], which improves the expected number of test paths by up to 5% compared to the Greedy algorithm.…”

Device-Parameter Estimation through IDDQ Signatures

“…For example, an adaptive substrate-bias control for each manufactured chip has been proposed to compensate for delay change resulting from threshold voltage variations [3]. In LSI testing, the idea of adaptive testing, in which a set of test paths is altered to apply the most suitable one for a chip, has been proposed [4]- [6]. Both of these techniques rely on the device-parameter estimations, such as threshold voltages of transistors, of an individual chip.…”