Path based approach for crosstalk delay analysis

Arvind, N.V.; Rajagopal, Karthik; Ajith, H.S.; Das, Subrangshu

doi:10.1109/icvd.2004.1261013

Cited by 5 publications

(5 citation statements)

References 7 publications

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“…Timing window discreteness was used for pessimism reduction in other papers [5][6][7] as well. Another work [8] considered aggressor noise injection timing against victim signal transition timing window.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk pessimism reduction with path base analysis

Tanaka

Nakashiro

2009

2009 10th International Symposium on Quality of Electronic Design

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Commercial crosstalk analysis tools are widely used for timing verification of LSI, but they analyze the worst case of crosstalk effect in any theoretical cases, which is really pessimistic. Some works have been done to reduce the pessimism based on deterministic method like logical correlation or timing window correlation. In this paper, a novel and practical crosstalk analysis introducing probability of simultaneous multiple aggressors' noise injection timing into crosstalk analysis methods with not only net based but also path based profiling is proposed. With the methods more than 50% pessimism reduction can be obtained in addition to net based approach.

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Section: Introductionmentioning

confidence: 99%

Crosstalk pessimism reduction with path base analysis

Tanaka

Nakashiro

2009

2009 10th International Symposium on Quality of Electronic Design

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“…(a) ( b ) The last constraints to be modified are (4), (7) and (8). Since their transformed functions are all the same type, we just explain it for constraint (4).…”

Section: Proofmentioning

confidence: 99%

“…GBA primarily relies on switching windows (between the minimum and maximum arrival times) of aggressors and victims for crosstalk calculation; even though, actual switching times are discrete. Hence, the timing windows are the major source of pessimism in crosstalk calculation [8].…”

Section: Gate-based Timing Analysismentioning

confidence: 99%

Post sign-off leakage power optimization

Abrishami

Lou

Qin

et al. 2011

Proceedings of the 48th Design Automation Conference

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With the scaling down of the CMOS technologies, leakage power is becoming an increasingly important issue in IC design. There is a trade-off between subthreshold leakage power consumption and clock frequency in the circuit; i.e., for higher performance, leakage power consumption must be sacrificed and vice versa. Meanwhile, timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. This power minimization can be done after the sign-off which is more accurate and realistic than if it is done before the sign-off. The available slack can be traded for leakage power minimization by footprint-based cell swapping and threshold voltage assignment. In this paper, we introduce our post sign-off leakage power optimization problem as a nonlinear mathematical program and solve it by using conjugate gradient (CG) method. We set up a novel transformation technique to manipulate the constraints of the optimization problem to be solved by CG. We show that by doing this optimization we can reduce the leakage power consumption by 34% on average in comparison with no power optimization after sign-off. All experiments are done on the real industrial designs.

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“…Thus the worst case path timing impact for each frequency group may be computed. [8] suggests that summing up the stage pushouts to compute the impact on the path timing is not realistic, and also that for each path, the signal arrival times (for the victims) can be treated as a discrete instead of a window. When multiple frequency groups are considered, we would get one such arrival time for each frequency group.…”

Section: Extension To Crosstalk Delay Analysismentioning

confidence: 99%

“…In equation (8) are correlation factors. If we assumed correlation between all nets in a path to be same, equation (8) can be re-written as,…”

Section: Table 1 Sorted Glitch At Netsmentioning

confidence: 99%

Crosstalk noise analysis at multiple frequencies

Shrivastava

Chandrasekar

18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design

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In SOC designs, it is common to have multiple clocks with some of them capable of operating at different frequencies. Crosstalk noise analysis uses switching information of nets in the form of timing windows to identify simultaneously switching aggressors. When clock frequencies change, the switching overlap relationship among nets also changes. Hence it is important to perform crosstalk analysis at all frequencies at which the chip may operate. In this paper we propose an approach to perform crosstalk analysis across multiple frequencies concurrently. We first present a method to obtain the worst crosstalk noise across all frequencies for each stage. Then we consider glitch propagation effects and build an efficient approach to analyze for crosstalk failures at all frequencies. We also discuss a method to guarantee functionality for a range of frequencies.

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Path based approach for crosstalk delay analysis

Cited by 5 publications

References 7 publications

Crosstalk pessimism reduction with path base analysis

Crosstalk pessimism reduction with path base analysis

Post sign-off leakage power optimization

Crosstalk noise analysis at multiple frequencies

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