Parylene-C passivated carbon nanotube flexible transistors

Abstract

Carbon nanotubes are extremely sensitive to the molecular species in the environment and hence require a proper passivation technique to isolate them against environmental variations for the realization of reliable nanoelectronic devices. In this paper, we demonstrate a parylene-C passivation approach for CNT thin film transistors fabricated on a flexible substrate. The CNT transistors are encapsulated with 1 and 3 m thick parylene-C coatings, and the transistor characteristics are investigated before and after passivation. Our findings indicate that thin parylene-C films can be utilized as passivation layers for CNT transistors and this versatile technique can be readily applied for the encapsulation of CNT devices such as field effect transistors, p-n diodes, and logic circuits fabricated on flexible substrates. © 2010 American Institute of Physics. ͓doi:10.1063/1.3499758͔Single-walled carbon nanotubes ͑SWNTs͒ with their unique physical, electrical, and mechanical properties are being considered as a potential replacement for existing semiconducting materials in flexible electronics. Their mobility can exceed 10 5 cm 2 / V s −1 , and they have large current carrying ͑10 9 A / cm 2 ͒ capability, higher ON/OFF ratios ͑Ͼ10 5 ͒ and extreme mechanical flexibility. 1 SWNT based field effect transistors ͑FETs͒ exhibit p-type behavior in the ambient environment, and they can be converted to n-type by doping e.g., polymer functionalization. 2 Carbon nanotube ͑CNT͒ flexible devices such as high frequency FETs, p-n diodes, and logic circuits have already been reported. 3 Their large surface area to volume ratios and extreme sensitivity to the molecular species in the environment ͑e.g., oxygen, moisture, etc.͒ can significantly affect the electrical properties of CNT transistors. [4][5][6] To isolate SWNT based flexible transistors from environmental factors, thin and flexible passivation layers need to be investigated prior to deployment of these devices in real world applications.Several groups have already explored passivation of CNT based devices with thin polymeric films yet had limited success. For example, Dai et al. 5 have reported a 1.7 m polymer ͓polymethyl-methacrylate ͑PMMA͔͒ coating for passivating CNT based transistors. When the PMMA encapsulated devices were exposed to a humid ambient, the electrical characteristics of the transistors changed due to permeation of water molecules through PMMA. Similarly, Zhang et al. 7 used SU-8/PMMA ͑2 m / 200 nm͒ to passivate their CNT FETs. After exposing their devices to an NO 2 environment for 1 h, they have noted that the gas molecules diffused through the SU-8/PMMA layer and caused variations in the transistor behavior. In addition to polymeric encapsulants, Kaminishi et al. and Kim et al. 8 ͑15 nm deposited using atomic layer deposition ͑ALD͒ at 300°C͒ layers as passivation layers for CNT FETs. The drawback with both Si 3 N 4 and ALD based deposition methods is that both materials are either deposited at or require annealing steps at elevated temperatures which lim...

Carbon Nanotube Macroelectronics for Active Matrix Polymer-Dispersed Liquid Crystal Displays

“…Detailed fabrication steps are described in the Methods. Note that we used parylene to passivate the transistors, and this passivation layer does not affect the transistor performance significantly (see Figure S1), which agrees with previous studies . This passivation layer is critical, as direct contact of PDLCs with the transistors in the integrated structure can degrade transistor performance.…”

“…Ti/Pd source (S) and drain (D) complete the transistor structure. We notice that a passivation layer of parylene is necessary to avoid performance degradation of the transistor in the integrated structure . For PDLC pixels, the PDLCs are sandwiched between two transparent indium tin oxide (ITO) electrodes.…”

“…Note that we used parylene to passivate the transistors, and this passivation layer does not affect the transistor performance significantly (see Figure S1), which agrees with previous studies. 33 This passivation layer is critical, as direct contact of PDLCs with the transistors in the integrated structure can degrade transistor performance. The transfer characteristics (I DS − V GS ) of a representative CNT-TFT after parylene passivation are presented in the red curve in Figure 3a, and the corresponding transconductance (g m − V GS ) is also plotted (blue) in the same graph.…”

Fully Integrated Indium Gallium Zinc Oxide NO2 Gas Detector

“…In the third chamber, the monomer gas was deposited and self-assembled to form the Parylene-C on top of the Si/SiO 2 /IGZO substrate at the 10 × 10 −6 mBar vacuum level. The CVD of Parylene-c is the best choice for the conformal coatings, 37 insulation, and pinhole-free surfaces. 38 In this case, the sample is not exposed to higher temperatures and there is no physical damage to the thin-film.…”

Competitive Impact of Nanotube Assembly and Contact Electrodes on the Performance of CNT-based FETs

“…As manipulating the hysteresis for volatile-memory applications can be attempted, the corresponding elimination becomes necessary for digital or analog devices. Considerable reports exist that attempt to understand the origin behind hysteresis and propose several methods to reduce it. − Identifying the environmental species as the origin for the hysteresis formation, distinct approaches for CNT passivation were proposed as solutions for the hysteresis reduction. It is important to emphasize that, during the passivation approaches reported so far, annealing between 150 and 200 °C was employed.…”