Partitioning Electrostatic and Mechanical Domains in Nanoelectromechanical Relays

Shavezipur, Mohammad; Harrison, Kimberly L.; Lee, William Scott; Mitra, Subhasish; Wong, H.-S. Philip; Howe, Roger T.

doi:10.1109/jmems.2014.2335157

Cited by 8 publications

(4 citation statements)

References 29 publications

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“…The fabrication process is demonstrated by constructing three-terminal, electrostatically-actuated NEM relays, similar in design to those presented by (Shavezipur et al 2015). The relay consists of a source electrode, drain electrode, gate electrode, and a flexible beam attached to the source electrode.…”

Section: Device Designmentioning

confidence: 99%

“…Figure 4 shows drain-source current versus gate-source voltage for a single device with SiN etch stop over six cycles. As described in Shavezipur et al (2015), the cantilever beam member attached to the source has a partitioned design which maximizes compliance at the base and minimizes bending near the gate electrode. This geometry reduces accidental shorting to the gate while maintaining low pull-in voltage.…”

Section: Device Testingmentioning

confidence: 99%

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Back-end-of-line compatible Poly-SiGe lateral nanoelectromechanical relays with multi-level interconnect

et al. 2016

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applications, power consumption issues have hindered development. An example of such power issues involves the size of pill cameras for colon inspections, which could be smaller and safer if smaller batteries could be used while maintaining adequate battery life (Darrin and Barth 2012). Another example involves the use of Field Programmable Gate Arrays (FPGAs) in aerospace applications, which is hindered by the large size and poor efficiency of FPGAs compared to ASICs (Chen et al. 2010). As a potential solution to these power issues, Nanoelectromechanical (NEM) relays are being investigated as logic components, due to their zero leakage current and steep subthreshold slope (Peschot et al. 2015). In configurations which can effectively leverage NEM relay's near-zero leakage current, integrated CMOS-relay systems show particular promise for reducing power. For example, it has been shown that hybrid CMOS-relay FPGA systems can reduce power by 10× and footprint by 2× compared to CMOS-only FPGA designs (Chen et al. 2010). For these reasons, NEM relays are described as potential "beyond CMOS" devices by the International Technology Roadmap for Semiconductors (ITRS 2011). However, industry adoption of NEM relays has been hindered by poor lifetime, high on-resistance, and CMOS-incompatible fabrication processes. Thus, the development of CMOS-compatible NEM relays with sufficiently low resistance and reliable behavior over many cycles would greatly accelerate their adoption in integrated electronic systems.NEM relays can be fabricated on top of CMOS-based devices if the relay fabrication meets all the criteria for back-end-of-line (BEOL) processing: low temperature deposition (<450 °C), low-stress materials, inclusion of diffusion barrier layers between silicon structures and buried aluminum interconnects to prevent spiking, and release processes that preserve interlayer dielectric layers. Previous Abstract Nanoelectromechanical (NEM) relays show promise in a wide variety of low power applications. NEM relays have near-zero leakage current, in contrast to the relatively high leakage current of nanoscale CMOS transistors, thus enabling hybrid CMOS-NEM relay systems that are more energy efficient. If NEM relays can be fabricated in the back-end-of-line (BEOL) metallization process, they can be added to a CMOS integrated circuit without adding significantly to the die area. In this paper, we demonstrate a CMOS BEOL-compatible fabrication process of NEM relays with protected, buried interconnects. The NEM relay processing steps are at temperatures below 425 °C and all mechanical and chemical processing steps are designed to avoid damage to underlying CMOS transistors. We demonstrate a lateral relay with buried interconnect that switches for more than 1000 cycles with resistances below 300 kΩ in nitrogen at atmospheric pressure.

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Section: Device Designmentioning

confidence: 99%

Section: Device Testingmentioning

confidence: 99%

Back-end-of-line compatible Poly-SiGe lateral nanoelectromechanical relays with multi-level interconnect

et al. 2016

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“…For NEM devices, these design tricks are prevented by the necessity to scale the area and dimensions of the device. Secondary pull-in is, in this case, driven by the device geometry and the environmental pressure [11]. These parameters were investigated in order to understand if the device can operate in a regime of high speed and low contact resistance without incurring in secondary pull-in and permanent stiction during operation.…”

Section: Introductionmentioning

confidence: 99%

Study of electrical breakdown and secondary pull-in failure modes for NEM relays

Ramezani¹,

Severi

Tilmans

et al. 2016

J. Micromech. Microeng.

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In this work, two common failure modes of nano-electro-mechanical (NEM) relays: (1) electrical breakdown and (2) stiction due to secondary pull-in were analyzed. These effects are dominant when dimensions of the device are scaled to the sub-micrometer scale. Like MEMS devices, design adjustments, such as introduction of dimples, cannot provide a solution. The geometrical parameters and working environment drive directly the occurrence of these failure modes. The beam length is the key parameter in driving the electrical breakdown while the distance of the gate to the drain, the beam thickness, and the actuation gap set the limits for secondary pull-in voltage. The analysis shows that these failure modes could be mitigated and a physical parameters design space could be identified to achieve NEM devices for high speed operation.

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“…The electrothermal transducer has been one of the popularly used manipulating techniques in micro-electromechanical systems (MEMS) − and in nano-electromechanical systems (NEMS), including nanomechanical resonators. − However, its high-power consumption is regarded as a considerable drawback: the generated thermal energy can easily escape to the thermal sink due to the high thermal conductivity of the resistive matter. This makes such devices impractical for use in various integrated circuit (IC) applications, whereas piezoelectric or electrostatic actuators − have been relatively well-established in emerging NEMS approaches for IC applications, emphasizing their great potential for low-voltage operation , and low-power consumption. − …”

mentioning

confidence: 99%

Nanomechanical Encoding Method Using Enhanced Thermal Concentration on a Metallic Nanobridge

Lee¹,

Choi²,

Choi³

et al. 2017

ACS Nano

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We present a fast, energy-efficient nano-thermomechanical encoding scheme for digital information storage and retrieval. Digital encoding processes are conducted by the bistable electrothermal actuation of a scalable nanobridge device. The electrothermal energy is highly concentrated by enhanced electron/phonon scattering and heat insulation in a sub-100 nm metallic layer. The efficient conversion of electrothermal energy into mechanical strain allows digital switching and programming processes within 60 ns at 0.75 V with a programming energy of only 54 pJ. Furthermore, this encoding scheme together with the thermally robust design enables data retention at temperatures up to 400 °C. These results suggest that the proposed nano-thermomechanical encoding method could contribute to low-power electronics and robust information storage/retrieval systems.

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Partitioning Electrostatic and Mechanical Domains in Nanoelectromechanical Relays

Cited by 8 publications

References 29 publications

Back-end-of-line compatible Poly-SiGe lateral nanoelectromechanical relays with multi-level interconnect

Back-end-of-line compatible Poly-SiGe lateral nanoelectromechanical relays with multi-level interconnect

Study of electrical breakdown and secondary pull-in failure modes for NEM relays

Nanomechanical Encoding Method Using Enhanced Thermal Concentration on a Metallic Nanobridge

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