Partitioning and optimization of high level stream applications for multi clock domain architectures

Brunet, Simone Casale; Bezati, Endri; Alberti, Claudio; Mattavelli, Marco; Amaldi, E.; Janneck, Jörn W.

doi:10.1109/sips.2013.6674501

Cited by 14 publications

(3 citation statements)

References 9 publications

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“…Furthermore, the room for improvement left, for instance, to scheduling strongly depends on the quality of the applied partitioning (i.e., low-quality partitioning configurations cannot be improved much by applying efficient scheduling). This property has been confirmed also for other, nondataflow domains [9,10]. The purpose of this work is to describe a new partitioning methodology to perform the design space exploration of dataflow program implementations.…”

Section: Introductionmentioning

confidence: 67%

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Michalska

Zufferey

Mattavelli

2016

Journal of Electrical and Computer Engineering

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The problem of partitioning a dataflow program onto a target architecture is a difficult challenge for any application design. In general, since the problem is NP-complete, it consists of looking for high quality solutions in terms of maximizing the achievable data throughput. The difficulty is given by the exploration of the design space which results in being extremely large for parallel platforms. The paper describes a heuristic partitioning methodology applicable to dynamic dataflow programs. The methodology is based on two elements: an execution model of the dynamic dataflow program which is used as estimation of the performance for the exploration of the large design space and several partitioning algorithms competing to lead to specific high quality solutions. Experimental results are validated with executions on a virtual platform.

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Section: Introductionmentioning

confidence: 67%

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Michalska

Zufferey

Mattavelli

2016

Journal of Electrical and Computer Engineering

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“…ShmuelWimer et al [11] explained design flow for Flip Flop using clock gating in the era of data driven mechanism in digital circuits. S.C Brunet et al [12] introduces multi clock domain for various circuits which are runs at various speed for optimizing the power consumption. W. Dobberpuhl et al [13] realized that a dual issue CMOS microprocessor for reducing power consumption.…”

Section: Manuscript Received On 14mentioning

confidence: 99%

Low Power Embedded SoC Design

2024

VLSI

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Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed.

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“…Structural power management: Within MPEG-RVC, a first tentative approach to structural power management has been targeted in [20] through the analysis of the causation trace of a Dataflow Process Network by applying then multi-clocking strategies. This technique, as far as we know, is still under refinement and has not been applied yet to reconfigurable systems.…”

Section: 31mentioning

confidence: 99%

Coarse‐grained reconfiguration: dataflow‐based power management

Palumbo

Raffo

2015

IET Computers & Digital Techniques

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Power reduction in modern embedded systems design is a challenging issue exacerbated by the complexity and heterogeneity of their architecture. In the field of Reconfigurable Video Coding (RVC), to challenge these issues and cut-down time to market, dataflow-based techniques have been adopted. In particular, to master management and composability of dynamically reconfigurable systems, the authors have developed the multi-dataflow composer. Nevertheless, despite the RVC offers several different tools, in its reference design framework power management is still an open issue. To make some steps forward towards filling this gap, in this study, they address power management for coarse-grained reconfigurable systems combining structural and dynamic strategies, both to be applied at the dataflow level. © The Institution of Engineering and Technology 2015

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Partitioning and optimization of high level stream applications for multi clock domain architectures

Cited by 14 publications

References 9 publications

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Low Power Embedded SoC Design

Coarse‐grained reconfiguration: dataflow‐based power management

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