Particle Swarm Optimization for Reconfigurable Sensor Electronics - Case Study: 3 Bit Flash ADC

Tawdross, Peter; König, Andreas

doi:10.1109/wises.2006.329121

Cited by 13 publications

(6 citation statements)

References 9 publications

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“…The assessment unit consists of the essential measurement setup required for evaluating the reconfigurable hardware performance. It can be performed extrinsically, intrinsically, or mixtrinsically [164]. The extrinsic evaluation is realized by the simulation-based measurement setup, while the intrinsic evaluation is based on the real hardware measurement setup.…”

Section: Assessment Unitmentioning

confidence: 99%

“…They used the genetic algorithm whose population contains both intrinsic and extrinsic individuals. In the former work at our institute [164], the concept of the mixtrinsic evaluation is extended differently by performing the complex measurements (phase margin, open-loop gain, etc.) extrinsically and executing the simple measurements (output voltage swing, and common-mode range) intrinsically, which helped to reduce the complexity of the assessment unit.…”

Section: Assessment Unitmentioning

confidence: 99%

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Integrated Sensor Electronic Front-Ends with Self-X Capabilities

Alraho

Zaman

Abd

et al. 2022

Chips

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The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.

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Section: Assessment Unitmentioning

confidence: 99%

Section: Assessment Unitmentioning

confidence: 99%

Integrated Sensor Electronic Front-Ends with Self-X Capabilities

Alraho

Zaman

Abd

et al. 2022

Chips

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“…For the synthesis of analog/RF circuits, a multi-objective differential evolution (DE) is discussed in [19]- [20]. Various dynamic reconfigurable circuits were designed using PSO [21]- [22]. In [23], analog circuits with low voltage and low power were designed with the help of Hierarchical PSO (HPSO).…”

Section: Introductionmentioning

confidence: 99%

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing

Shreeharsha,

Siddharth,

Vasantha

et al. 2023

IEEE Access

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This work introduces a Partition Bound Particle Swarm Optimization (PB-PSO) algorithm to enhance convergence rates in analog circuit optimization. Two new parameters, ζ 1 and ζ 2 , are incorporated to adaptively update particle velocities based on iteration numbers. The parameter ζ 1 depends on the nonlinear convergence factor (α) and the number of iterations, N . The results indicate that ζ 1 's optimal value occurs with α = 4. ζ 2 partitions iterations into two regions, aiding local and global search. The PB-PSO algorithm, implemented in Python, demonstrates higher convergence rates than existing methods, with successful designs verified through Cadence-Virtuoso circuit simulations. The proposed PB-PSO algorithm converges in 15 and 13 iterations for differential amplifier and two-stage op-amp respectively. For a case study of two-stage amplifier, it achieves a gain of 60.4 dB with a phase margin of 79.76 • , meeting input specifications within constraints. The figure of merit was then evaluated using the obtained parameters, which turns out to be 0.275 V −2 . INDEX TERMS Particle swarm optimization (PSO), analog circuit sizing, low power, operational amplifiers, constrained optimization.

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“…PSO is used for dynamic reconfiguration of field‐programmable analog circuits . PSO is also utilized for reconfigurable sensor electronics in . Low‐power and low‐voltage analog circuits have been designed using Hierarchical particle swarm optimization (HPSO) .…”

Section: Introductionmentioning

confidence: 99%

Soft computing‐based approach for optimal design of on‐chip comparator and folded‐cascode op‐amp using colliding bodies optimization

Kar

Mandal

et al. 2016

Int J Numerical Modelling

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This paper presents an efficient approach for the optimal designs of two analog circuits, namely complementary metal oxide semiconductor) two-stage comparator with p-channel metal oxide semiconductor input driver and n-channel input and folded-cascode operational amplifier using a recently proposed meta-heuristic-based optimization algorithm named as colliding bodies optimization (CBO). It is a multi-agent algorithm that does not depend upon any internal control parameter, making the algorithm extremely simple. The main objective of this paper is to optimize the metal oxide semiconductor (MOS) transistors' sizes using CBO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. Simulation Program with Integrated Circuit Emphasis simulation has been carried out by using the optimal values of MOS transistors' sizes and other design parameters to validate that CBO-based design is satisfying the desired specifications. Simulation results demonstrate that the design specifications are closely met and the required functionalities are achieved. The simulation results also confirm that the CBO-based approach is superior to the other algorithms in terms of MOS area and performance parameters like gain, power dissipation, etc., for the examples considered.For CBO, number of colliding bodies (CBs) is taken as 10 and dimensions of each CB is defined as X Comparator = [SR, A vd , V IC(min) , V IC(max) ]. So, the dimension of the optimization problem is 4. 878 B. P. DE ET AL.

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Particle Swarm Optimization for Reconfigurable Sensor Electronics - Case Study: 3 Bit Flash ADC

Cited by 13 publications

References 9 publications

Integrated Sensor Electronic Front-Ends with Self-X Capabilities

Integrated Sensor Electronic Front-Ends with Self-X Capabilities

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing

Soft computing‐based approach for optimal design of on‐chip comparator and folded‐cascode op‐amp using colliding bodies optimization

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