Partially reconfigurable entropy encoder for multi standards video adaptation

Marques, Nicolas; Rabah, Hassan; Dabellani, Eric; Weber, S.

doi:10.1109/isce.2011.5973879

Cited by 8 publications

(1 citation statement)

References 6 publications

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“…4, constraining some of the reconfigurable resources provided by current Xilinx FPGAs such as CLB, BRAM and DSP blocks. Reconfigurable regions may be either rectangular (the most basic shape that can be defined in Xilinx PlanAhead, see case 1) or L-shaped (designed to optimize resource utilization by the task, also referred to as internal fragmentation) [16]. Reconfigurable regions height must respect clock domains (case 2).…”

Section: Rr Determination Per Taskmentioning

confidence: 99%

Design space exploration for partially reconfigurable architectures in real-time systems

Duhem¹,

Muller²,

Aubry³

et al. 2013

Journal of Systems Architecture

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In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with Error Correcting Code and showed that partial reconfiguration may lead to an area ✩ This document is a collaborative effort.

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Section: Rr Determination Per Taskmentioning

confidence: 99%