Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm

Xie, Yu; Yu, Wen-Yue; Zhang, Ning; Chen, He; Xie, Yi-Zhuang

doi:10.1109/dft59622.2023.10313538

Cited by 1 publication

(3 citation statements)

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“…The conventional approach for managing fault tolerance or self-healing in literature typically relies on redundancy or replication [13]. These methods require significant resource consumption, which may be deemed unacceptable given certain constraints.…”

Section: Traditional Fault Diagnosis Methodsmentioning

confidence: 99%

“…Traditional ways to address fault tolerance (FT) or self-healing are often based on redundancy or algorithm. Triple modular redundancy (TMR) [11], Reduced Precision Redundancy (RPR) [12], Partial TMR [13], Algorithm-Based Fault-Tolerance (ABFT), and concurrent error detection (CED) are commonly used as information redundancy methods. The method for ABFT-FFT takes advantage of convolution theorem is proposed in [14].…”

Section: Introductionmentioning

confidence: 99%

“…Electronics 2024,13, x FOR PEER REVIEW 18 of 21 (2) Training epoch number corresponding to the maximum accuracy: From the Training Epoch Number of Max Accuracy column, it can be observed that different methods require different training epoch numbers to achieve the maximum accuracy. For example, the FFT-ResNet18 method reached the highest accuracy of 99.55% at the 144th training epoch.…”

mentioning

confidence: 99%

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Fault Classification and Diagnosis Approach Using FFT-CNN for FPGA-Based CORDIC Processor

Xie,

Chen,

Zhuang

et al. 2023

Electronics

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Within the realm of digital signal processing and communication systems, FPGA-based CORDIC (Coordinate Rotation Digital Computer) processors play pivotal roles, applied in trigonometric calculations and vector operations. However, soft errors have become one of the major threats in high-reliability FPGA-based applications, potentially degrading performance and causing system failures. This paper proposes a fault classification and diagnosis method for FPGA-based CORDIC processors, leveraging Fast Fourier Transform (FFT) and Convolutional Neural Networks (CNNs). The approach involves constructing fault classification datasets, optimizing features extraction through FFT to shorten the time of diagnosis and improve the diagnostic accuracy, and employing CNNs for training and testing of faults diagnosis. Different CNN architectures are tested to explore and construct the optimal fault classifier. Experimental results encompassing simulation and implementation demonstrate the improved accuracy and efficiency in fault classification and diagnosis. The proposed method provides fault prediction with an accuracy of more than 98.6% and holds the potential to enhance the reliability and performance of FPGA-based CORDIC circuit systems, surpassing traditional fault diagnosis methods such as Sum of Square (SoS).

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Section: Traditional Fault Diagnosis Methodsmentioning

confidence: 99%