Partial TMR for Improving the Soft Error Reliability of SRAM-Based FPGA Designs

Keller, Andrew; Wirthlin, Michael

doi:10.1109/tns.2021.3070856

Cited by 9 publications

(3 citation statements)

References 23 publications

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“…In a recent work [15], Keller et al explored partial TMR as a means to reduce the overhead. They selectively replicate some components, but not others, and evaluate several selection approaches under neutron radiation and fault injection.…”

Section: Related Workmentioning

confidence: 99%

Analyzing Reduced Precision Triple Modular Redundancy Under Proton Irradiation

García-Astudillo

Entrena

Lindoso

et al. 2022

IEEE Trans. Nucl. Sci.

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This work analyzes the performance of the Reduced Precision Redundancy (RPR) error mitigation technique using the Fast Fourier Transform (FFT) as a case study. To this purpose, several configurations of an FFT IP design were implemented in FPGA using Reduced Precision TMR and tested under proton irradiation and fault injection. The cross-section, the sensitivity to Common-Mode Failures (CMFs) and the signal-to-noise ratio of these configurations were evaluated. The results of the radiation experiments and fault injection campaigns are in agreement and show that the Reduced Precision TMR technique may be used as an alternative to TMR if small errors can be tolerated, as it has a good performance in terms of error correction capabilities, area usage and sensitivity to critical errors.

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Section: Related Workmentioning

confidence: 99%

Analyzing Reduced Precision Triple Modular Redundancy Under Proton Irradiation

García-Astudillo

Entrena

Lindoso

et al. 2022

IEEE Trans. Nucl. Sci.

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“…Compared with a permanent error, a non-permanent error is present only part of the time, and may occur randomly [25]. For example, an alpha particle hit, or cosmic ray ionization may change a value stored in a memory bit cell (such as DRAM or SRAM) [27]; the value can be corrected by rewriting the correct value. The data in the memory cells also returns to the normal value after the circuit system is rebooted, because a transient error does not occur again, so non-permanent [26].…”

Section: Error Modelmentioning

confidence: 99%

Analysis of Approximate adders with single functional error

Huang,

Thulasiraman,

Almurib

et al. 2024

Preprint

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“…In low cost or low power cases, this large overhead may not be acceptable. To alleviate this overhead, some authors have studied partial error mitigation solutions that perform a selection of the components to replicate [12]. Alternatively, approximate redundant solutions have been proposed.…”

Section: Background and Related Workmentioning

confidence: 99%

Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique

et al. 2022

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Error mitigation techniques, such as Triple Modular Redundancy, introduce very large overheads. To alleviate this overhead, approximate techniques can be used. In this work we propose a novel approximate error mitigation technique based on using redundant circuits with lower resolution. As a representative case study, the approach is demonstrated for a Fast Fourier Transform, for which an optimized architecture is proposed. The approach is validated through fault injection. Experimental results show that Reduced Resolution Redundancy can significantly reduce the overhead and achieve an excellent error mitigation performance and a low sensitivity to uncorrectable errors.

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Partial TMR for Improving the Soft Error Reliability of SRAM-Based FPGA Designs

Cited by 9 publications

References 23 publications

Analyzing Reduced Precision Triple Modular Redundancy Under Proton Irradiation

Analyzing Reduced Precision Triple Modular Redundancy Under Proton Irradiation

Analysis of Approximate adders with single functional error

Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique

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