Partial SOI as a HV platform technology for Power Integrated Circuits

Holke, Alexander; Antoniou, Marina; Udrea, F.

doi:10.1109/ispsd46842.2020.9170051

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…The positive voltage on the substrate needs to be carefully isolated from a grounded heat sink. X-FAB is currently offering an 180nm SOI technology with a PSOI option up to 200V [13], [14], [15] and has recently released the 400V rated devices. This technology is based on a p-substrate with the substrate sitting at a ground potential and therefore attaching a heat sink, or heat convection materials (such as Copper) is straightforward.…”

Section: A History and Commercial Implementationsmentioning

confidence: 99%

“…This stems from the commonly used fly-back converter architecture, with internal reflections resulting in such high voltage overshoot. However, with new more complex architectures with integrated power supplies using multiple floating switches, there is no internal overvoltage requirement and the voltage rating can thus be safely set to maximum voltage of 375V [15]. In addition, the loop inductance in integrated PICs is also very small, therefore there is practically no voltage overshoot from the gate driver to the power switches and hence, no additional overvoltage requirements.…”

Section: B Applicationsmentioning

confidence: 99%

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High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

Antoniou

Udrea

Tee³

et al. 2022

IEEE Trans. Electron Devices

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Partial SOI (PSOI) is a widely recognized technology suitable for High Voltage (HV) architectures for Power Integrated Circuits (PICs). Despite the added process complexity compared to SOI RESURF, this technology offers a wider range of voltage ratings due to the action of the depletion layer in the Handle Wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-dimensional designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low on-state resistance and reduced selfheating are essential requirements. This work presents a PSOI technology platform with voltage ratings ranging from 45 to 400V while providing low on-state resistance, good hot carrier injection stability as well as Electrostatic Discharge (ESD) capability of the HV devices. For example, for a 375V rated LDMOSFET, this technology achieves an on-state resistance of 1435mΩ.mm 2 , an over 50% improvement compared to the state-of-the-art SOI technologies while maintaining competitive reliability.

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Section: A History and Commercial Implementationsmentioning

confidence: 99%

Section: B Applicationsmentioning

confidence: 99%

High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

Antoniou

Udrea

Tee³

et al. 2022

IEEE Trans. Electron Devices

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“…To achieve high efficiency and small chip size, on-chip HV switches with low area-specific on-resistance and low parasitic capacitances are required. Besides HV lateral SJ-MOSFETs [29], more and more HV technologies offer HV lateral SJ-LIGBTs [30]. As part of this work, both options are explored.…”

Section: B Hv-switch Typesmentioning

confidence: 99%

A Resonant One-Step 325 V to 3.3–10 V DC–DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques

Rindfleisch

Wicht

2021

IEEE J. Solid-State Circuits

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This work presents a self-timed resonant highvoltage (HV) dc-dc converter in HV CMOS silicon-on-insulator (SOI) with a one-step conversion from 100-325 V input down to a 3.3-10 V output, optimized for applications below 500 mW, such as IoT, smart home, and e-mobility. Unlike bulky power modules, the HV converter is fully integrated, including an on-chip power stage, with only one external inductor (10 µH) and capacitor (470 nF). It reaches a high power density of 752 mW/cm 3 , an overall peak efficiency as high as 81%, and a light-load efficiency of 73.2% at 5 V and 50 mW output. HV loss-reduction techniques are presented and experimentally confirmed to offer an efficiency improvement of more than 32%. Integrated HV insulated gate bipolar transistors (IGBTs) are discussed and implemented as an attractive alternative to conventional integrated HV power switches, resulting in ∼20% smaller area at lower losses.

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