Partial scan at the register-transfer level

Steensma, J.; Catthoor, Francky; Man, H. De

doi:10.1109/test.1993.470662

Cited by 17 publications

(1 citation statement)

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“…Chickermane et al [33] showed that the use of RT-level information to select scan flip-flops results in significantly better performance when compared to techniques limited to gate-level information only. Steensma et al [34] proposed an efficient partial-scan methodology applicable to data paths described at the RT level. The method is based on eliminating loops by making existing registers scannable or by adding extra transparent scan registers.…”

Section: B High-level Dft Techniquesmentioning

confidence: 99%

Nonscan design-for-testability techniques using RT-level design information

Dey

Potkonjak²

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents nonscan design-for-testability (DFT) techniques applicable to register-transfer (RT)-level data path circuits. Knowledge of high-level design information, in the form of the RT-level structure, as well as the functions of the RT-level components is utilized to develop effective nonscan DFT techniques. Instead of conventional techniques of selecting flip-flops (FF's) to make controllable/observable, execution units (EXU's) are selected using the EXU S-graph introduced in this paper. Controllability/observability points can be implemented using register files and constants.We introduce the notion of k k k-level controllable and observable loops and demonstrate that it suffices to make all the loops k k k-level controllable/observable, k k k> > >0, to achieve very high test efficiency.

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Section: B High-level Dft Techniquesmentioning

confidence: 99%