Partial run-time reconfiguration of FPGA for computer vision applications

Birla, Manashvi; Vikram, Karimella

doi:10.1109/ipdps.2008.4536518

Cited by 7 publications

(4 citation statements)

References 5 publications

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“…(1) The traditional advantage of using a DAG computation model over a linear chain is that it permits tasks to be executed in parallel on different processors. In current FPGA systems, the response time is dominated by FPGA reconfiguration delays and not computation time [1,5,6]. This, along with the limited number of FPGAs available on a board, minimizes the traditional advantage of working directly with a DAG.…”

Section: Discussion Of Design Contextmentioning

confidence: 99%

“…Gajjala Purna and Bhatia [5] reported that the hardware execution time for a set of four applications was on the order of tens of microseconds, while a single reconfiguration requires 242 milliseconds on the RACE architecture. More recently, Birla and Vikram [6] reported that an integral image computation was executed in 12.36 s with reconfiguration times ranging from 3.309 to 52.944 ms (depending on the configuration clock frequency). A feature extraction and classification computation had an execution time of 8.66 s with reconfiguration times ranging from 3.392 to 54.268 ms.…”

Section: Introductionmentioning

confidence: 99%

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Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

2013

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This paper considers the problem of scheduling a chain of n coarse-grained tasks on a linear array of k reconfigurable FPGAs with the objective of primarily minimizing reconfiguration time. A high-level meta-algorithm along with two detailed meta-algorithms (GPRM and SPRM) that support a wide range of problem formulations and cost functions is presented. GPRM, the more general of the two schemes, reduces the problem to computing a shortest path in a DAG; SPRM, the less general scheme, employs dynamic programming. Both meta algorithms are linear in n and compute optimal solutions. GPRM can be exponential in k but is nevertheless practical because k is typically a small constant. The deterministic quality of this meta algorithm and the guarantee of optimal solutions for all of the formulations discussed make this approach a powerful alternative to other metatechniques such as simulated annealing and genetic algorithms.

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Section: Discussion Of Design Contextmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

2013

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“…A realtime video processing system using PR is described in [Bhandari et al 2009], where different image processing filters are implemented in the same reconfigurable region to reduce resource requirements and power consumption. In [Birla and Vikram 2008], the AdaBoost algorithm for human detection is implemented on a Virtex-4 FPGA using PR. Two computationally intensive tasks, integral image computation and feature extraction/decision, are alternately implemented in a single PRR, saving significant area.…”

Section: System Cost Reductionmentioning

confidence: 99%

FPGA Dynamic and Partial Reconfiguration

2018

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Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.

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“…Here a processor configures a PR region with different classification modules to evaluate the input pattern. In [98], the Ad-aBoost algorithm for human detection is implemented on a Virtex-4 FPGA using PR. Two computationally intensive tasks, integral image computation and feature extraction/decision, are alternately implemented in a single PR region.…”

Section: Machine Learningmentioning

confidence: 99%

Design automation for partially reconfigurable adaptive systems

Vipin¹

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Adaptive systems have the ability to respond to environmental conditions, by modifying their processing at runtime. While this is easy to do in software systems, modern algorithms can be computationally expensive, requiring powerful processors. At the same time hardware is not as flexible. Field programmable gate arrays (FPGAs) are recognised as being suitable for adaptive systems implementation, due to their flexibility and high performance. New hybrid FPGA platforms which integrate able processors with reconfigurable fabric provide a new platform to further explore hardware reconfigurability. The use of partial reconfiguration (PR) on FPGAs to implement adaptive systems has been proposed many times in the literature. However the design process for partially reconfigurable systems is complex and requires specialist knowledge on behalf of the application designer. Hence, it has remained a rarely used capability outside of academic circles. We propose a new approach to leverage PR within adaptive systems, by integrating with, rather than circumventing, supported vendor tool flows, while automating many of the steps that have made such designs more difficult in the past. This makes it possible for system designers with less FPGA expertise to use PR when designing adaptive systems.

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Partial run-time reconfiguration of FPGA for computer vision applications

Cited by 7 publications

References 5 publications

Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

FPGA Dynamic and Partial Reconfiguration

Design automation for partially reconfigurable adaptive systems

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