Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Abstract

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited 4 times lower Ioff than modified S-FinFET called RFinFET with more improved DIBL characteristics while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved DIBL and Ioff characteristics as gate channel length decreased.