Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Abstract

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower I off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I off characteristics as gate channel length decreased.Keywords: gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (I on ); off-current (I off ); subthreshold slope (SS); threshold voltage (V TH ); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); technique for the buried insulator under the cell transistor [7,8]. We analyzed electrical characteristics of this proposed device and compared them with those of conventional S-FinFETs of the same size. We also showed the optimized parameters of the buried insulator using a three-dimensional (3D) device simulator in sub-30 nm cell size [9]. The device described in this paper has reliable source/drain (S/D) doping concentration with a Gaussian profile. The simulator is well tuned to predict DRAM cell transistor leakage distribution [10,11]. Device StructureThe partial isolation type S-FinFET (Pi-FinFET) is a structure with a buried insulator at a certain depth from the storage node of a conventional S-FinFET. Figure 1a shows a 3D schematic of a Pi-FinFET. Silicon film thickness, buried insulator thickness, and L in , as shown in Figure 1a,b, are defined as the distance from the contact surface of the storage node to the buried insulator, the thickness of the buried insulator in the direction perpendicular to the channel, and the distance from the side gate oxide to the buried insulator, respectively. L g , L side , L ov_xj , and L ov_side represent gate channel length, the length of the side-gate in the direction parallel to the channel, the overlapped length of the side-gate and S/D doping region shown in Figure 1a, and the side-channel width shown in Figure 1c, respectively. When L side and L ov_xj are increased, the width of the overlap region of the gate and the S/D region will also increase. The n + poly gate with a gate work function of 4.2 eV was applied. L g , L side , L ov_side and the recessed depth are 30 nm, 42 nm, 10 nm, and 100 nm, respectively. RFinFET is the modified S-FinFET with a structure in which the overlap region between the side-gate and the S/D region is removed [5]. Therefore, the Pi-FinFETs proposed in this paper can be divided into Pi-SFinFET and Pi-RFinFET depending on the presence or absence of the overlap region between the side-gate and the S/D region. Namely, in...

S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s

“…This is because the deep penetration of the buried insulator limits the lateral PDW in the narrow silicon layer between the gate and drain regions and this lateral PDW becomes narrow. Our previous study confirmed that if the ratio of L in to L g is 50% or below, the I off increases [14]. However, high electric field due to the narrow PDW is formed only in the upper side of the buried insulator and the rest of the region has a smaller electric field than Pi-FinFETs that have 20nm L in (66.7%).…”

“…The buried insulator parameters, i.e., silicon film thickness, buried insulator thickness, and L in were set as 20, 100 and 20 nm, respectively. These parameters were chosen to minimize leakage current while maintaining a high on-current as possible [14]. An n+ poly gate with a gate work function of 4.6 eV was applied.…”

“…However, if the I off in S-FinFETs is not minimized, there will be significant drawbacks in their application for DRAM technology. To address this issue, Pi-FinFETs (Pi-SFinFET, Pi-RFinFET) that have a partial isolation region under the storage node of S-FinFETs (SFinFET, RFinFET) have been proposed [12][13][14]. However, in Pi-FinFETs fabricated using an isotropic dry etching technique where the insulator is buried under the cell transistor [15,16], the buried insulator can cause an interface trap between itself and the drain region [17].…”

Nanoelectronic Materials, Devices and Modeling: Current Research Trends

“…New concepts of data storage and memory devices are another focus of this issue. A partial isolation type saddle-FinFET has been proposed for sub-30 nm DRAM applications [9]. A new method for neural networks based on resistive switches has been proposed for pattern storage and recognition [10].…”

Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT) for a Sub-20 nm DRAM Cell Transistor

“…The structures presented in this paper are fabricated using a 3D device simulation (sentaurus TCAD). These device structures use a Gaussian distribution of the doping concentration in order to provide a reliable doping profile [25][26][27].…”