Partial evaluation based triple modular redundancy for single event upset mitigation

Katkoori, Srinivas; Islam, Sheikh Ariful; Kakarla, Sujana

doi:10.1016/j.vlsi.2020.11.002

Cited by 3 publications

(2 citation statements)

References 32 publications

(55 reference statements)

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“…For this reason newer and newer solutions of MV are still developed, both on logical and technological level. New TMR solution, more and more immune to SEU are also created as: Temporal, Partial or Partitioned TMR [17], [18], [19], [20].…”

Section: Configuration Readbackmentioning

confidence: 99%

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Węgrzyn¹,

Jamro²,

Dąbrowska-Boruch³

et al. 2021

Preprint

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This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

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Section: Configuration Readbackmentioning

confidence: 99%

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Węgrzyn¹,

Jamro²,

Dąbrowska-Boruch³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…For this reason, newer solutions of MV are still being developed, both at the logical and technological levels. New TMR solutions, increasingly immune to SEUs, are also created as temporal, partial, or partitioned TMR [18][19][20][21].…”

Section: Configuration Readbackmentioning

confidence: 99%

Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

et al. 2021

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Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

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Estimation of the parameters of triple modular redundancy system under step partially accelerated life tests using Frechet distribution

Issa,

Kneehr

2024

BIO Web Conf.

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Triple modular redundancy system (TMR) is repetition of important components or functions of the system. It aims to increase the reliability and reducing the failure rate. This study is focused on the estimating of the distribution’s parameters of the "TMR system" under the partly life test with gradual stress, as it included every component in the system that follows The Frechete distribution. This research aimed to analysis the reliability of this triple modular system. The optimal time for stress change was determined using two criteria according to the accelerated stress strategy under the new distribution, as well as estimating the reliability of the system by using the maximum likelihood (MLE) method. The efficiency of the " MLE" in estimate the parameters of the new distribution is one of the most important conclusions in this study. Therefore, the design of the "TMR” system can have a lengthy lifetime and higher safety, reducing the risks of unexpected failure and the economic losses.

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Partial evaluation based triple modular redundancy for single event upset mitigation

Cited by 3 publications

References 32 publications

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Estimation of the parameters of triple modular redundancy system under step partially accelerated life tests using Frechet distribution

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