Partial Bitstream 2-D Core Relocation for Reconfigurable Architectures

Rossmeissl, Chad; Sreeramareddy, Adarsha; Akoglu, Ali

doi:10.1109/ahs.2009.41

“…[7,8]). In [66], a relocation method aimed at tiled devices is presented; the method permits relocation of functional units of a pre-determined size, which incorporate communication buses. To allow for the heterogeneous nature of modern FPGA, the authors define reconfigurable regions only over pure logic sections (thus excluding elements like memory and multipliers).…”

Section: Free Functional Unit Placement and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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“…[7,8]). In [66], a relocation method aimed at tiled devices is presented; the method permits relocation of functional units of a pre-determined size, which incorporate communication buses. To allow for the heterogeneous nature of modern FPGA, the authors define reconfigurable regions only over pure logic sections (thus excluding elements like memory and multipliers).…”

Section: Free Functional Unit Placement and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

0

View full text Add to dashboard Cite

A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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“…The faster and more efficient approaches use a hardware unit that allows manipulating the configuration header on the fly without losing configuration speed [3]. The advanced concepts [4][5] also allow to relocate PRMs in 2 dimensions instead of the 1 dimensional slot based approaches. In summary, runtime module relocation is a well established technique to reduce the configuration overhead and to improve the runtime flexibility.…”

Section: Motivation and Related Workmentioning

confidence: 99%

Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs

Schuck

¹

,

Haetzer

²

,

Hübner

³

et al. 2011

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PHD Forum

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Module-based partial reconfiguration of FPGAs offers great possibilities for runtime flexibility. It enables hardware tasks to swap in and out the design without interruption of the entire system. In this context the techniques of module relocation and the 2-dimensional reconfiguration have been successfully applied in order to reduce the storage requirement for partial bit-streams and to shorten the reconfiguration times significantly. Besides the adaptation on functional level, multiple clock domains and dynamic frequency scaling are key techniques to achieve an adaptation on power and performance level as well. However, current approaches of module relocation provide no support for designs with multiple clock domains. In this paper we present a new method of online clock network routing, which solves this problem. The concept is based on a "on the fly" manipulation of configuration bits which determine the clk-inputs of the single slices. The method is implemented in hardware in order to maximize configuration performance. Our results show that a memory saving of 66% for an example design can be achieved while the original reconfiguration speed could be maintained. Figures for hardware usage are also given.

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Partial Bitstream 2-D Core Relocation for Reconfigurable Architectures

Cited by 11 publications

References 29 publications

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs

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