PARDIS: A programmable memory controller for the DDRx interfacing standards

Abstract

Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable-a proven technique that has seen wide use in other control tasks ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware.This paper presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable memory controller that can meet the performance requirements of a high-speed DDRx interface. The proposed controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the performance of PARDIS comes within 8% of an ASIC implementation of these techniques in every case; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6-17% and reduces DRAM energy by 9-22% over four existing memory controllers.

A reconfigurable real-time SDRAM controller for mixed time-criticality systems

“…The PARDIS programmable memory controller [4] is reconfigurable in several respects. Two small processors with custom instruction set architectures take the role of memory controller, their firmware determining the command scheduling policy, address mapping, refresh scheduling and power management.…”

Managing DRAM Latency Divergence in Irregular GPGPU Applications

“…In addition, compared to a GPU that consumes upwards of 200W of power, the memory controller consumes very little power. For example, a complex, programmable memory controller with 128KB of storage and multiple ALU-like pipelined paths [10] has been shown to consume only 152mW. Our proposals are significantly simpler than the PARDIS controller and hence will not have any noticeable effect on system power consumption.…”

DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework

“…DRAMSys also assists to configure the address mapping of memory controllers that target ASIC implementations, such as Refs. [39], [40], [41]. Figure 9 shows the results of the simulation of the 3 different address mappings: Standard, Custom and XOR with DRAMSys that is configured to model the Xilinx MIG, as well as the archieved bandwidth on the real hardware (XOR HDL).…”