Parasitic Capacitances and Inductances for Multilevel Interconnections on GaAs-Based Integrated Circuits

Abstract

A computer-efficient algorithm to determine the parasitic capacitances and inductances associated with high-density multilevel interconnections on GaAs-based integrated circuits is presented. The self and coupling interconnection capacitances have been determined by an efficient and more flexible network analogue method developed for the finite dimension interconnection configurations as well as by the method of moments in conjunction with a Green's function appropriate for the geometry of the interconnection lines. The Green's function was obtained by using the method of multiple images. The results include the fringing fields as well as the shielding by the neighboring interconnections. For a given set of the interconnection dimensions, the algorithm takes less than 30 seconds of computer processing time on a mainframe computer equipped with a math co-processor. The algorithm has been used to study the dependences of the interconnection capacitances and inductances on the interconnection parameters such as their length, width, interlevel distances, separation and the substrate thickness for a system of parallel single-, bi-, and tri-level interconnections printed on or embedded in the GaAs substrate.

Analysis of crossing interconnections on GaAs-based VLSICs

“…The self and coupling capacitances used in the model include the fringing fields and also the shielding effect of the neighboring interconnects [3] , [4]. The software developed has been used to study the dependece of the crosstalk voltage and signal delay on the interconnect dimensions like length, width, separation and interlevel distance.…”