Parametric Critical Path Analysis for Event Networks With Minimal and Maximal Time Lags

Pinxten, Joost van; Geilen, Marc; Hendriks, Martijn; Basten, Twan

doi:10.1109/tcad.2018.2857360

Cited by 3 publications

(2 citation statements)

References 23 publications

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“…Our approach simultaneously discovers the reachable scheduling results and the symbolic conditions under which they are reachable. e convexity of parametric problems is o en based on the resulting parametric a ne expressions, as in [7], [10], and [16]. In these works, the throughput expressions and a ne schedules are determined for data-ow graphs and iteration vectors respectively.…”

Section: Related Workmentioning

confidence: 99%

“…e makespan of a schedule results from its critical paths. A parametrized expression for the makespan of a schedule for a given speci c parameter combination can be determined by the algorithm presented in [16]. Such critical path expressions of the parametric scheduling result determine the performance slopes inside the regions.…”

Section: Evaluating Points Strictly Inside a Decision Regionmentioning

confidence: 99%

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Parametric Scheduler Characterization

Pinxten

Geilen

Basten

2019

ACM Trans. Embed. Comput. Syst.

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Section: Related Workmentioning

confidence: 99%

Section: Evaluating Points Strictly Inside a Decision Regionmentioning

confidence: 99%

Parametric Scheduler Characterization

Pinxten

Geilen

Basten

2019

ACM Trans. Embed. Comput. Syst.

Self Cite

View full text Add to dashboard Cite

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Construction of Multi-Project Network Planning Based on BOM and Its Resource Leveling

2021

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For the manufacturing project of large and complex equipment, due to the large number of activities, and the complex structure of the project, there are often cases where multiple projects are going on at the same time, which might make the project's network planning extremely difficult. Based on the analysis of the BOM and classification characteristics of complex manufacturing equipment, this paper proposed an innovative method, which can decompose and transform the component units based on the BOM, so that the BOM of the complex project can be hierarchically optimized and simplified. Then it can be transformed into project network plan by Petri net unit transformation method, so as to realize the decomposition and arrangement of multiple project plans. On this basis, aiming at the problem of resource leveling in multi-project planning management, this paper proposes a genetic algorithm, which provides a transformation method for resource optimization. In addition, this paper presents a new genetic coding method and improves the crossover operation. Case study shows that the algorithm can solve the resource balance problem of multi-project planning successfully. Finally, in order to verify the effectiveness of the algorithm, the proposed algorithm is compared with the other two algorithms intuitively and quantitatively.

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A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches

Luo

Xing

et al. 2022

Applied Sciences

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As semiconductor technology evolves, computing platforms attempt to integrate hundreds of processing cores and associated interconnects into a single chip. Network-on-chip (NoC) technology has been widely used for data exchange centers in recent years. As the core element of the NoC, the round-robin arbiter provides fair and fast arbitration, which is essential to ensure the high performance of each module on the chip. In this paper, we propose a low-latency fair switch arbiter (FSA) architecture based on the tree structure search algorithm. The FSA uses a feedback-based parallel priority update mechanism to complete the arbitration within the leaf nodes and a lock-based round-robin search algorithm to guarantee global fairness. To reduce latency, the FSA keeps the lock structure only at the leaf node so that the complexity of the critical path does not increase. Meanwhile, the FSA achieves a critical path with only O(log4N) delay by using four input nodes in parallel. The latency of the proposed circuit is on average 22.2% better than the existing fair structures and 8.1% better than the fastest arbiter, according to the synthesis results. The proposed architecture is well suited for high-speed network-on-chip switches and has better scalability for switches with large numbers of ports.

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Parametric Critical Path Analysis for Event Networks With Minimal and Maximal Time Lags

Cited by 3 publications

References 23 publications

Parametric Scheduler Characterization

Parametric Scheduler Characterization

Construction of Multi-Project Network Planning Based on BOM and Its Resource Leveling

A Low-Latency Fair-Arbiter Architecture for Network-on-Chip Switches

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