Parameterized Time Warp (PTW): An Integrated Adaptive Solution to Optimistic PDES

Palaniswamy, Avinash C.; Wilsey, Philip A.

doi:10.1006/jpdc.1996.0114

Cited by 15 publications

(8 citation statements)

References 15 publications

(18 reference statements)

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“…Many metrics have been proposed in the literature (Ball and Hoyt 1990;Palaniswamy and Wilsey 1996;Fleischmann and Wilsey 1995;Reiher and Jefferson 1990;Tay, Teo, and Kong 1997). Since rollbacks occur because certain LPs advance too far ahead of other LPs in virtual time, it is natural to consider LVT in determining useful work.…”

Section: Useful Work Metricsmentioning

confidence: 98%

“…In their scheme, event scheduling is throttled based on distance from GVT. However, using LVT for this purpose can unintentionally prevent the simulator from uncovering hidden parallelism in the application model (Palaniswamy and Wilsey 1996). For example, consider a simulation with two LPs executing on separate PEs.…”

Section: Useful Work Metricsmentioning

confidence: 99%

“…In Time Warp, the concept of utilization is entirely different. Time Warp aggressively uses all available CPU resources throughout the duration of a simulation, so it must instead use the concept of "useful work" (Palaniswamy and Wilsey 1996) to detect and balance the critical path. Turbo Boost and Turbo CORE are unable to detect imbalances in Time Warp simulations and thus may not be able to correctly detect and accelerate the critical path.…”

Section: Introductionmentioning

confidence: 99%

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Using DVFS to optimize time Warp simulations

Child¹,

Wilsey²

2012

Proceedings Title: Proceedings of the 2012 Winter Simulation Conference (WSC)

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Some emerging high performance many-core chips have support to enable software control of an individual core's operating frequency (and voltage). These controls can potentially be used to optimize execution for either performance (accelerating the critical path) or power savings (green computing). In Time Warp parallel simulators using the Virtual Time synchronization paradigm, some cores may be executing events that are well off the critical path and likely to be undone. In this work, we explore the adjustment of operating frequencies of cores executing on and off the critical path to reduce rollback and power consumption, while maintaining or, in some cases, enhancing performance.

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Section: Useful Work Metricsmentioning

confidence: 98%

Section: Useful Work Metricsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Using DVFS to optimize time Warp simulations

Child¹,

Wilsey²

2012

Proceedings Title: Proceedings of the 2012 Winter Simulation Conference (WSC)

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“…Run-time tuning to optimize performance has been successfully applied to a number of subalgorithms of a Time Warp synchronized parallel simulation [13]. Most significantly it has been used for: (i) sizing the checkpoint interval of an LP [14], [15], [16], (ii) selecting the cancellation strategy for an LP [17], and (iii) for event scheduling [18], [19], [20], [21].…”

Section: B Time Warpmentioning

confidence: 99%

Dynamically Adjusting Core Frequencies to Accelerate Time Warp Simulations in Many-Core Processors

Child

Wilsey

2012

2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation

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Time Warp synchronized parallel discrete event simulators are organized to operate asynchronously and aggressively without explicit synchronization between the concurrently executing simulators. In place of an explicit synchronization mechanism, the concurrent simulators maintain a common virtual clock model and implement a rollback/recovery mechanism to restore causal order when out-of-order events are detected. When the critical path of execution of the simulation is balanced across these parallel simulators, this can result in a highly effective, lightweight synchronization mechanism. However, imbalances in the workload across the parallel simulators can result in excessive rollback at some nodes and ultimately result in an overall slowing of the simulation as prematurely computed and transmitted events are processed. On small shared memory multi-core systems, a lowest timestamp first scheduling policy can effectively balance the workload. However, on larger many-core chips, conventional load balancing and workload migration will once again become necessary. Fortunately, emerging many-core chips contain some interesting features that can potentially be exploited to improve the performance of parallel simulations. For example, the Intel Single-chip Cloud Computer (SCC) provides mechanisms that a running application can use to adjust the frequency/voltage of different regions (called islands) of the chip. These islands are network and processing core centric and thus, in a Time Warp simulation, one can increase the frequency of the cores executing threads on the critical path (those experiencing infrequent rollback) and decrease the frequency of the cores executing threads off the critical path (those experiencing excessive rollback). This paper investigates the run-time control and adjustment of core frequency in an AMD Phenom II X6 multi-core processor to explore and demonstrate that the dynamic run-time control of core frequency can sometimes improve the performance of a Time Warp synchronized parallel simulation.

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“…However, the successful utilization of the Time Warp mechanism has been plagued by the time and space overheads of rollback such as: state saving, state restoration and event re-processing. Numerous modifications/optimizations to Time Warp have been proposed and analyzed [1,4,8,10,15,19,23,29]. Many of these studies have focused on techniques to dynamically adjust a simulator's runtime parameters.…”

Section: Introductionmentioning

confidence: 99%