Parameterized loop tiling

Abstract

Loop tiling is a widely used program optimization that improves data locality and enables coarse-grained parallelism. Parameterized tiled loops, where the tile sizes remain symbolic parameters until runtime, are quite useful for iterative compilers and autotuners that produce highly optimized libraries and codes. Although it is easy to generate such loops for (hyper-) rectangular iteration spaces tiled with (hyper-) rectangular tiles, many important computations do not fall into this restricted domain. In the past, parameterized tiled code generation for the general case of convex iteration spaces being tiled by (hyper-) rectangular tiles has been solved with bounding box approaches or with sophisticated and expensive machinery. We present a novel formulation of the parameterized tiled loop generation problem using a polyhedral set called the outset . By reducing the problem of parameterized tiled code generation to that of generating standard loops and simple postprocessing of these loops, the outset method achieves a code generation efficiency that is comparable to existing code generation techniques, including those for fixed tile sizes. We compare the performance of our technique with several other tiled loop generation methods on kernels from BLAS3 and scientific computations. The simplicity of our solution makes it well suited for use in production compilers—in particular, the IBM XL compiler uses the inset-based technique introduced in this article for register tiling. We also provide a complete coverage of parameterized tiling of perfect loop nests by describing three related techniques: (i) a scheme for separating full and partial tiles; (ii) a scheme for generating tiled loops directly from the abstract syntax tree representation of loops; (iii) a formal characterization of parameterized loop tiling using bilinear forms and a Symbolic Fourier-Motzkin Elimination (SFME)-based parameterized tiled loop generation method.

Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays

“…Renganarayanan et al [13], [14] proposed a systematic technique for transforming an n-dimensional loop into a 2n-dimensional tiled loop for rectangular tiles covering a given polyhedral loop iteration space. The tile sizes can be parametric, but only one tiling level is considered and the generated tiled loop code is assumed to be executed sequentially.…”

“…Proof: From Eq (14) we know that the latency of a linear schedule λ is determined by the difference between maximal and the minimal time step plus one:…”

Symbolic parallelization of loop programs for massively parallel processor arrays

“…Therefore, to enable run-time feedback and dynamic program adaption, symbolic (parameterized) tiling has recently received attention in the parallelizing compiler community. Here, Renganarayana et al [10], [11] proposed a systematic technique for transforming an n-dimensional loop into a 2n-dimensional tiled loop for rectangular tiles covering a given polyhedral loop iteration space. New in this approach is that the tile sizes can be parametric.…”

“…. + κ n · b n ∀d ∈ D (11) where each κ i ∈ N 0 and e i denotes the i-th unit vector. For a given tight intra-tile schedule candidate λ J , a minimal-latency schedule λ = (λ J λ K ) may be found by considering only the following set of transformed dependency vectors…”

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

“…Loop tiling is a classic loop transformation technique to enhance data locality [16]- [20]. In this paper, we employ the loop tiling technique for a novel objective.…”