Parameterizable implementation of full search block matching algorithm using FPGA for real-time applications

Mohammadzadeh, Mohammad; Eshghi, Mohammad; Azadfar, M.M.

doi:10.1109/iccdcs.2004.1393383

Cited by 7 publications

(9 citation statements)

References 10 publications

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“…In spite of this, [6] and [9] represents most competitive architectures for 16 × 16, but [9] doesn't reach RT, and to increase the hardware using 16 SAD16 units multiply by 30 the hardware amount. For 8 × 8 model [5] and [6] are most efficient. Since a 16 × 16 block size search area is four times bigger than 8 × 8, to present a 16 × 16 architecture for [5] can be interesting to know how the hardware cost increases.…”

Section: Comparisonmentioning

confidence: 98%

“…For 8 × 8 model [5] and [6] are most efficient. Since a 16 × 16 block size search area is four times bigger than 8 × 8, to present a 16 × 16 architecture for [5] can be interesting to know how the hardware cost increases. In [6] the hardware increases linearly, and it's multiply by 4 when search area is multiply by 4.…”

Section: Comparisonmentioning

confidence: 98%

“…Mohammadzadeh et al [5] Also implements the AS1 architecture. An 8 × 8 solution is proposed and how to extend to 16 × 16 block is not explained.…”

Section: Recent Architectures In Fpgamentioning

confidence: 99%

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Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA

Olivares¹,

Benavides²,

Hormigo

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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Block matching motion estimation takes a great part of the processing time for video encoding. To accelerate this process is must to reach real time video coding. The best motion vector is obtained by full-search block matching algorithm which has to be usually implemented by hardware. In recent years, several FPGA based designs have been proposed since these devices support high number of process elements in parallel mode. In this paper a survey of recent architectures to perform the full-search block matching algorithm in FPGAs is presented. A further comparison on terms of frames per second reached, hardware cost in CLB slices and system frequency is presented.

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Section: Comparisonmentioning

confidence: 98%

Section: Comparisonmentioning

confidence: 98%

See 1 more Smart Citation

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA

Olivares¹,

Benavides²,

Hormigo

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

show abstract

“…[7] proposed an FPGA architecture to implement parallel computation of FSBM. Systolic array and novel OnLine Arithmetic (OLA) based designs for FSBM were proposed in [8] and [9], respectively. Customizable low-power FPGA cores were proposed by [10].…”

Section: Introuctionmentioning

confidence: 99%

“…Customizable low-power FPGA cores were proposed by [10]. The aforementioned FSBM architectures can be divided into two categories, namely, FPGA [7,8,9,10,11,17] and ASIC [4,15,18,2,3,20,5,19,13,1,6]. This work uses FPGA technology to implement a high-performance ME hardware with due consideration to (a) processing speed and (b) silicon area.…”

mentioning

confidence: 99%

Speed-area optimized FPGA implementation for Full Search Block Matching

Ghosh

Saha

2007

2007 25th International Conference on Computer Design

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IntrouctionRapid growth in High-Definition (HD) digital video applications has lead to an increased interest in portable HDquality encoder design. HD-compatible MPEG2 MP@HL encoder uses Full Search Block Matching Algorithm (FS-BMA) based Motion Estimation (ME). The ME module accounts for more than 80% of the computational complexity of a typical video encoder. Moreover, the power consumption of an FSBM-based encoder is prohibitively high, particularly for portable implementations. Hence, efficient ME processor cores need to be designed to realize portable HDTV video encoders.Parameterizable FSBM ASIC design to solve the input bandwidth problem by using on-chip line buffers was proposed in [15]. [18] proposed a family of modular VLSI architectures which allow sequential inputs but perform parallel processing with 100 percent efficiency. A systolic mapping procedure to derive FSBM architectures was proposed in [4]. The designs of ([2], [20]) and [5] focused on the reduction of pin counts by sharing memory units and 2-dimensional data reuse, respectively. [19] improved the memory bandwidth by using an overlapped data flow of search area which increased the processing element (PE) utilization. A low-latency high-throughput tree architecture for FSBM was proposed in [3]. Both [13] and [1] proposed low-power architectures based on removal of unnecessary computations. Finally, a novel low-power parallel tree FSBM architecture was proposed in [6], which exploited the spatial data correlations within parallel candidate block searches for data sharing and thus effectively reduces data access bandwidth and power consumption. [7] proposed an FPGA architecture to implement parallel computation of FSBM. Systolic array and novel OnLine Arithmetic (OLA) based designs for FSBM were proposed in [8] and [9], respectively. Customizable low-power FPGA cores were proposed by [10]. The aforementioned FSBM architectures can be divided into two categories, namely, FPGA [7,8,9,10,11,17] and ASIC [4,15,18,2,3,20,5,19,13,1,6]. This work uses FPGA technology to implement a high-performance ME hardware with due consideration to (a) processing speed and (b) silicon area. Almost all aforementioned VLSI architectures optimize any one of these parameters. The novelty of the proposed architecture lies in its combined optimization of the aforementioned conflicting design requirements. The proposed hardware uses an initially-split pipeline to reduce processing cycles for each MB and thus increases the throughput. In addition, this design requires less number of adders and only one Absolute Difference (AD) PE, which drastically reduces the silicon area when compared to other existing designs. The pixels of the search regions have been organized in memory banks such that two sets of 128-bit (16 8-bit pixels) data can be accessed in each clock cycle.Section 2 gives an overview of FSBM-based motion estimation. Section 3 presents a brief discussion on SAD modifications and describes the proposed FSBM hardware. The implementation and comparative...

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