8th International Conference on Power Electronics - ECCE Asia 2011
DOI: 10.1109/icpe.2011.5944405
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Parameter design of a five-level inverter for PV systems

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Cited by 19 publications
(6 citation statements)
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“…In (13), the power semiconductor conduction and switching losses, cond P and sw P respectively, are calculated as the sum of the conduction and switching losses of the individual power switches and diodes forming the power section of the PV inverter. For the calculation of the power semiconductor conduction losses, cond P , the PV inverter power switches and diodes are considered as voltage sources with resistors connected in series [24]:…”
Section: Pv Inverter Modeling For Optimizationmentioning
confidence: 99%
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“…In (13), the power semiconductor conduction and switching losses, cond P and sw P respectively, are calculated as the sum of the conduction and switching losses of the individual power switches and diodes forming the power section of the PV inverter. For the calculation of the power semiconductor conduction losses, cond P , the PV inverter power switches and diodes are considered as voltage sources with resistors connected in series [24]:…”
Section: Pv Inverter Modeling For Optimizationmentioning
confidence: 99%
“…After the GA-based optimization process described in § 2 has been accomplished, the optimal value of the LCLfilter damping resistor, dr R , is calculated according to (10) using the resulting optimal values of L , g L and f C . The values of cond P and sw P in (13) have been calculated using the equations of the power-loss model presented in [24] as a function of according to [21,22].…”
Section: Design Optimization Examplementioning
confidence: 99%
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“…Changes may have been made to this work since it was submitted for publication. To generate the switching pulses, a variety of strategies have been presented to generate the output voltage with reduced harmonics and simultaneously regulate the FC voltage of the converter such as carrier-based PWM [4], modified triangular carrier-based PWM [5], optimized pulse pattern [6] and selective harmonic elimination PWM (SHE-PWM) [7], [8]. In these methods, to generate switching pulses, the dc-link capacitor voltages are considered to be balanced or the calculation is carried out based on balanced condition.…”
Section: Introductionmentioning
confidence: 99%
“…The redundancy in the switching states of the FC-based ANPC converter allows the voltage across FC to be regulated. To generate the switching pulses, a variety of strategies has been presented to generate the output voltage with reduced harmonics and simultaneously regulate the FC voltage of the converter such as Carrier-based PWM [4], modified triangular carrier-based PWM [5], selective harmonic elimination PWM (SHE-PWM) [6] and optimized pulse pattern [7]. The use of five-level vector PWM in three phase applications using switching redundancies to control FC voltages are presented in [8]- [10].…”
Section: Introductionmentioning
confidence: 99%