Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector

Saidani, Tarik; Lacassagne, Lionel; Falcou, Joel; Tadonki, Claude; Bouaziz, Samir

doi:10.1007/978-3-642-19448-1_10

Cited by 8 publications

(8 citation statements)

References 14 publications

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“…Accelerated implementation is fundamentally investigated by Wu, Lam and Srikanthan in [6], and by Tadonki et al in [36]. An implementation on the CELL processor is provided and discussed by Saidani et al in [35]. The last two contributions also provide a qualitative and quantitative study of tiling.…”

Section: Related Work On Harris Detector Implementationmentioning

confidence: 99%

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Harris corner detection on a NUMA manycore

Haggui

Tadonki

Lacassagne

et al. 2018

Future Generation Computer Systems

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Corner detection is a key kernel for many image processing procedures including pattern recognition and motion detection. The latter, for instance, mainly relies on the corner points for which spatial analyses are performed, typically on (probably live) videos or temporal flows of images. Thus, highly efficient corner detection is essential to meet the real-time requirement of associated applications. In this paper, we consider the corner detection algorithm proposed by Harris, whose the main work-flow is a composition of basic operators represented by their approximations using 3 × 3 matrices. The corresponding data access patterns follow a stencil model, which is known to require careful memory organization and management. Cache misses and other additional hindering factors with NUMA architectures need to be skillfully addressed in order to reach an efficient scalable implementation. In addition, with an increasingly wide vector registers, an efficient SIMD version should be designed and explicitly implemented. In this paper, we study a direct and explicit implementation of common and novel optimization strategies, and provide a NUMA-aware parallelization. Experimental results on a dual-socket INTEL Bradwell-E/EP show a noticeably good scalability performance.

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Section: Related Work On Harris Detector Implementationmentioning

confidence: 99%

“…The SIMD part is left to the compiler (the native one for each considered architecture), and shared memory parallelism is implemented with OpenMP (through classical directives. Other studies of Harris corner detection and its applications can be found in [35,36,37,38,39].…”

Section: Introductionmentioning

confidence: 99%

Harris corner detection on a NUMA manycore

Haggui

Tadonki

Lacassagne

et al. 2018

Future Generation Computer Systems

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“…loads from unaligned memory addresses, so that each value of the neighborhood can be available as a SIMD vector. To limit the number of such loads, a technique called the register rotation technique [16] is often used. This technique allows filter-like algorithms to perform only one load per iteration, swapping neighborhood values as the algorithm goes forward.…”

Section: Sliding Window Iteratormentioning

confidence: 99%

Boost.SIMD

Esterie

Falcou

Gaunard³

et al. 2014

Proceedings of the 2014 Workshop on Programming Models for SIMD/Vector Processing

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SIMD extensions have been a feature of choice for processor manufacturers for a couple of decades. Designed to exploit data parallelism in applications at the instruction level, these extensions still require a high level of expertise or the use of potentially fragile compiler support or vendor-specific libraries. While a large fraction of their theoretical accelerations can be obtained using such tools, exploiting such hardware becomes tedious as soon as application portability across hardware is required. In this paper, we describe BOOST.SIMD, a C++ template library that simplifies the exploitation of SIMD hardware within a standard C++ programming model. BOOST.SIMD provides a portable way to vectorize computation on Altivec, SSE or AVX while providing a generic way to extend the set of supported functions and hardwares. We introduce a C++ standard compliant interface for the users which increases expressiveness by providing a high-level abstraction to handle SIMD operations, an extension-specific optimization pass and a set of SIMD aware standard compliant algorithms which allow to reuse classical C++ abstractions for SIMD computation. We assess BOOST.SIMD performance and applicability by providing an implementation of BLAS and image processing algorithms.

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“…Différentes implantations ont été évaluées en détail dans (Saidani et al, 2008), seuls les résultats de la version Halfpipe sont analysés ici. Les SPE du Cell ayant été conçus pour faire du calcul SIMD et non du calcul scalaire, les versions scalaires sont toutes inefficaces, le gain global ×214 n'est donc pas significatif.…”

Section: Le Cellunclassified

Parallélisation d'opérateurs de TI : multi-cœurs, Cell ou GPU ?

Pedron¹,

Laguzet²,

Saidani³

et al. 2010

Traitement du signal

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Cet article présente une évaluation des performances de 14 architectures actuelles : 8 processeurs généralistes, 5 GPU ainsi que le processeur Cell. L'algorithme retenu est l'opérateur de détection de points d'intérêt de Harris car représentatif des algorithmes de traitement d'images régulier bas niveau. À travers différentes transformations algorithmiques et optimisations logicielles adaptées à chaque architecture, cet article guide l'utilisateur dans le choix d'une architecture parallèle et évalue l'impact des optimisations afin d'avoir une implantation en adéquation avec l'architecture selon deux critères : le temps de calcul et la consommation énergétique. ABSTRACT. This article deals with a performance analysis of current architectures : 8 general purpose processors, 5 graphic processing units and the Cell processor. The Harris salient points detection operator has been selected as representative of low level image processing. Through the presentation of algorithmic transforms and software optimization tuned to each architecture, the goal of this paper is to guide the user in chosing a parallel architecture and to assess how different transformations impact so as to get an architecture optimized implementation for two constraints: execution time and power consumption.

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Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector

Cited by 8 publications

References 14 publications

Harris corner detection on a NUMA manycore

Harris corner detection on a NUMA manycore

Boost.SIMD

Parallélisation d'opérateurs de TI : multi-cœurs, Cell ou GPU ?

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