Parallelization in co-compilation for configurable accelerators-a host/accelerator partitioning compilation method

Becker, Juergen; Hartenstein, Reiner W.; Herz, Michael; Nageldinger, U.

doi:10.1109/aspdac.1998.669393

Cited by 14 publications

(9 citation statements)

References 13 publications

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“…Thus, they can not further accelerate an application since they do not benefit from the ability of the coarse-grain hardware for speeding-up applications [5,6,24]. Hardware/software partitioning approaches for systems composed by a processor and a coarse-grain reconfigurable array were presented in [25,26]. Fine-grain reconfigurable hardware was not considered in those systems.…”

Section: Partitioning For Reconfigurable Architecturesmentioning

confidence: 99%

A method for partitioning applications in hybrid reconfigurable architectures

Galanis

Milidonis

Theodoridis

et al. 2005

Des Autom Embed Syst

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In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.

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Section: Partitioning For Reconfigurable Architecturesmentioning

confidence: 99%

A method for partitioning applications in hybrid reconfigurable architectures

Galanis

Milidonis

Theodoridis

et al. 2005

Des Autom Embed Syst

View full text Add to dashboard Cite

show abstract

“…This alternative paradigm uses data counters instead, which are located in auto-sequencing data memory banks [Herz et al 2002]. A configware compiler for RC (e.g., Becker et al [1998]) creates a tailored pipe network to be configured into the rDPA. This is not just an abstraction since the pipe network is physically implemented at the RT level.…”

Section: Introductionmentioning

confidence: 99%

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

Ayala-Rincón

Llanos

Jacobi

et al. 2006

ACM Trans. Des. Autom. Electron. Syst.

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Many algebraic operations can be efficiently implemented as pipe networks in arrays of functional units such as systolic arrays that provide a large amount of parallelism. However, the applicability of classical systolic arrays is restricted to problems with strictly regular data dependencies yielding only arrays with uniform linear pipes. This limitation can be circumvented by using reconfigurable systolic arrays or reconfigurable data path arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative reconfigurable systolic architectures can be explored and powerful tools are needed to model and evaluate them. Well-known rewriting-logic environments such as ELAN and Maude can be used to specify and simulate complex application-specific integrated systems. In this article we propose a methodology based on rewriting-logic which is adequate to quickly model and evaluate reconfigurable architectures (RA) in general and, in particular, reconfigurable systolic architectures. As an interesting case study we apply this rewriting-logic modeling methodology to the space-efficient treatment of the Fast-Fourier Transform (FFT). The FFT prototype conceived in this way, has been specified and validated in VHDL using the Quartus II system.

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“…One of the most challenging issues for reconfigurable computing systems is the development of mapping methods able to reduce the growing gap between design capacity and technology [1]. New field-programmable gate arrays (FPGAs) with millions of logic gates are becoming available, but high-level methods still lack.…”

Section: Introductionmentioning

confidence: 99%

Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines

Cardoso

Neto

2001

Field-Programmable Logic and Applications

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Abstract. This paper presents new achievements on the automatic mapping of abstract algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled with one or more memories. The compilation flow exposes operation-and functional-level parallelism, and speculative execution. Such expositions are efficiently represented by an hierarchical model. In order to take full advantage of such representation, the scheduling scope is significantly improved by merging basic blocks at loop boundaries and by considering the parallel execution of exposed concurrent loops. The paper describes the scheduling technique, shows a study on the impact of the merge operation, and reveals the improvements achieved when the exposed parallelism is fully satisfied.

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Parallelization in co-compilation for configurable accelerators-a host/accelerator partitioning compilation method

Cited by 14 publications

References 13 publications

A method for partitioning applications in hybrid reconfigurable architectures

A method for partitioning applications in hybrid reconfigurable architectures

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines

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