Parallel workload analysis in SMP platform: a new modelling approach to infer the hardware efficiency for remote sensing application

Yi, Guo; Kanellou, Eleni; Cardona, Luis Andres; Rius, A.; Ferrer, Carles

doi:10.1117/12.821549

Cited by 3 publications

(5 citation statements)

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“…Different possibilities to design this post-processing system have been explored. One of the first explorations was a Multi-Processor System-on-Chip (MPSoC) using symmetric multiprocessing (SMP) scheme [4], but due to limitations with bus congestion, other alternatives were explored in order to achieve the required performance. Figure1 presents the complete system, which includes the post-processing part.…”

Section: Target Application and Related Workmentioning

confidence: 99%

“…These waveforms are composed of complex values (I and Q), and the application needs to process these data under a time constraint. To do this, several architectural implementations have been designed in our group [4] [5], all of them using FPGA devices and mainly focused on the time restrictions to guarantee the performance. Therefore, the objective of this work is to introduce PR capabilities to study their influence in area taking into account performance restrictions.…”

Section: Introductionmentioning

confidence: 99%

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Partial reconfiguration of a peripheral in an FPGA-based SoC to analyse performance-area behaviour

Cardona

Guo

Ferrer³

2011

VLSI Circuits and Systems V

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Systems on Chip (SoC) are present in a wide range of applications. This diversity in addition with the quantity of critical variables involved in their design process becomes it as a great challenging topic. FPGAs have consolidated as a preferred device to develop and prototype SoCs, and consequently Partial Reconfiguration (PR) has gained importance in this approach. Through PR it is possible to have a section of the FPGA operating, while other section is disabled and partially reconfigured to provide new functionality. In this way hardware resources can be time-multiplexed and therefore it is possible to reduce size, cost and power. In this case we focus on the implementation of a SoC, in an FPGA-based board, with one of its peripherals being a reconfigurable partition (RP). Inside this RP different hardware modules defined as reconfigurable modules (RM) can be configured. Thus, the system is suitable to have different hardware configurations depending on the application needs and FPGA limitations, while the rest of the system continues working. To this end a MicroBlaze soft-core processor is used in the system design and a Virtex-5 FPGA board is utilized to its implementations. A remote sensing application is used to explore the capabilities of this approach. Identifying the section(s) of the application suitable of being time-shared it is possible to define the RMs to place inside the RP. Different configurations were carried out and measurements of area were taken. Preliminary results of the performance-area utilisation are presented to validate the improvement in flexibility and resource usage.

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Section: Target Application and Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Partial reconfiguration of a peripheral in an FPGA-based SoC to analyse performance-area behaviour

Cardona

Guo

Ferrer³

2011

VLSI Circuits and Systems V

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“…Finally, the numerical simulations are intended to illustrate the parallel computing improvements that the proposed HTPCP can achieve. Fig.8 depicts a SMP architecture which we proposed in our previous work [9]. The system integrated with multi-LEON3 processor with its own caches and Memory Management Unit (MMU), but shared the main memory.…”

Section: B Memory Hierarchy In Pmmentioning

confidence: 99%

“…Taking into account time-to-market issues and rapid prototype development, a shared memory Symmetric Multiprocessing (SMP) mounted with embedded OS appears as the first option to explore. However bus-based SMP has limited scalability due to bus congestion and shared memory [9]. With the advent of multi-core processor system, Networkon-Chip (NOC) provides separation architecture between computation and communication.…”

Section: Introductionmentioning

confidence: 99%

HTPCP: GNSS-R multi-channel cross-correlation waveforms post-processing solution for GOLD-RTR instrument

Guo

Atienza

Rius

et al. 2010

2010 NASA/ESA Conference on Adaptive Hardware and Systems

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“…However, bus-based SMPs have limited scalability due to bus congestion and shared memory issues. 3 The advent of network-on-a-chip (NOC) separates computation and communication architectures. Compared with symmetric multiprocessing, NOC enhances system throughput and scalability.…”

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confidence: 99%

Heterogeneous transmission and parallel computing platform for remote sensing

Guo¹,

Ruis²,

Ribó³

et al. 2011

SPIE Newsroom

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Parallel workload analysis in SMP platform: a new modelling approach to infer the hardware efficiency for remote sensing application

Cited by 3 publications

References 0 publications

Partial reconfiguration of a peripheral in an FPGA-based SoC to analyse performance-area behaviour

Partial reconfiguration of a peripheral in an FPGA-based SoC to analyse performance-area behaviour

HTPCP: GNSS-R multi-channel cross-correlation waveforms post-processing solution for GOLD-RTR instrument

Heterogeneous transmission and parallel computing platform for remote sensing

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