Parallel Programming with Migratable Objects: Charm++ in Practice

Acun, Bilge; Gupta, Abhishek; Jain, Nikhil; Langer, Akhil; Menon, Harshitha; Mikida, Eric; Ni, Xiang; Robson, Michael P.; Sun, Youwen; Totoni, Ehsan; Wesolowski, Lukasz; Kalé, Laxmikant V.

doi:10.1109/sc.2014.58

Cited by 124 publications

(68 citation statements)

References 36 publications

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“…There are many parallel programming languages that over-decompose the total work into many small tasks. Some examples of such distributed parallel programming languages are Charm++ [6], AMPI [23], etc. For shared memory machines, Cilk [11], OpenMP [16], etc.…”

Section: Programming Systemsmentioning

confidence: 99%

Energy-efficient computing for HPC workloads on heterogeneous manycore chips

Langer

Totoni

Palekar

et al. 2015

Proceedings of the Sixth International Workshop on Programming Models and Applications for Multicores and Manycores

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Power and energy efficiency is one of the major challenges to achieve exascale computing in the next several years. While chips operating at low voltages have been studied to be highly energy-efficient, low voltage operations lead to heterogeneity across cores within the microprocessor chip. In this work, we study chips with low voltage operation and discuss programming systems, and performance modeling in the presence of heterogeneity. We propose an integer linear programming based approach for selecting optimal configuration of a chip that minimizes its energy consumption. We obtain an average of 26% and 10.7% savings in energy consumption of the chip for two HPC mini-applications -miniMD and Jacobi, respectively. We also evaluate the energy savings with execution time constraints, using the proposed approach. These energy savings are significantly more than the savings by sub-optimal configurations obtained from heuristics.

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Section: Programming Systemsmentioning

confidence: 99%

Energy-efficient computing for HPC workloads on heterogeneous manycore chips

Langer

Totoni

Palekar

et al. 2015

Proceedings of the Sixth International Workshop on Programming Models and Applications for Multicores and Manycores

Self Cite

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“…To enable malleable jobs, two components are critical -a smart job scheduler, which decides when and which jobs to shrink or expand, and a parallel runtime system which provides dynamic shrink and expand capability to the job. We rely on existing runtime support for malleable jobs in Charm++ [20]- [22]. In Charm++, malleability is achieved by dynamically redistributing compute objects to processors at runtime.…”

Section: Data Center and Job Capabilitiesmentioning

confidence: 99%

Maximizing Throughput of Overprovisioned HPC Data Centers Under a Strict Power Budget

Sarood

Langer

Gupta

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

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101

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Abstract-Building future generation supercomputers while constraining their power consumption is one of the biggest challenges faced by the HPC community. For example, US Department of Energy has set a goal of 20 MW for an exascale (10 18 flops) supercomputer. To realize this goal, a lot of research is being done to revolutionize hardware design to build power efficient computers and network interconnects. In this work, we propose a software-based online resource management system that leverages hardware facilitated capability to constrain the power consumption of each node in order to optimally allocate power and nodes to a job. Our scheme uses this hardware capability in conjunction with an adaptive runtime system that can dynamically change the resource configuration of a running job allowing our resource manager to re-optimize allocation decisions to running jobs as new jobs arrive, or a running job terminates.We also propose a performance modeling scheme that estimates the essential power characteristics of a job at any scale. The proposed online resource manager uses these performance characteristics for making scheduling and resource allocation decisions that maximize the job throughput of the supercomputer under a given power budget. We demonstrate the benefits of our approach by using a mix of jobs with different powerresponse characteristics. We show that with a power budget of 4.75 MW, we can obtain up to 5.2X improvement in job throughput when compared with the SLURM scheduling policy that is power-unaware. We corroborate our results with real experiments on a relatively small scale cluster, in which we obtain a 1.7X improvement.

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“…In our experiments, we found that this has negligible impact since only a small fraction of the execution time would need conservative configurations. Note that in some rare scenarios, the structure can slightly change (such as two SEBs running in switched orders in CHARM++ [41], [42]), but these variations can be handled conservatively as well. Moreover, the runtime goes to a conservative cache configuration when there were too many mistakes in the DFA's predictions.…”

Section: B Generalizationmentioning

confidence: 99%

Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy

Totoni

Torrellas

Kalé

2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-The cache hierarchy often consumes a large portion of a processor's energy. To save energy in HPC environments, this paper proposes software-controlled reconfiguration of the cache hierarchy with an adaptive runtime system. Our approach addresses the two major limitations associated with other methods that reconfigure the caches: predicting the application's future and finding the best cache hierarchy configuration. Our approach uses formal language theory to express the application's pattern and help predict its future. Furthermore, it uses the prevalent Single Program Multiple Data (SPMD) model of HPC codes to find the best configuration in parallel quickly. Our experiments using cycle-level simulations indicate that 67% of the cache energy can be saved with only a 2.4% performance penalty on average. Moreover, we demonstrate that, for some applications, switching to a software-controlled reconfigurable streaming buffer configuration can improve performance by up to 30% and save 75% of the cache energy.

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Parallel Programming with Migratable Objects: Charm++ in Practice

Cited by 124 publications

References 36 publications

Energy-efficient computing for HPC workloads on heterogeneous manycore chips

Energy-efficient computing for HPC workloads on heterogeneous manycore chips

Maximizing Throughput of Overprovisioned HPC Data Centers Under a Strict Power Budget

Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy

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