Parallel Programming of an Ionic Floating-Gate Memory Array for Scalable Neuromorphic Computing

Fuller, Elliot James; Keene, Scott T.; Melianas, Armantas; Wang, Zhongrui; Agarwal, Sapan; Li, Yiyang; Tuchman, Yaakov; James, Conrad D.; Marinella, Matthew; Salleo, Alberto; Talin, A. Alec

doi:10.1149/ma2019-02/27/1241

Cited by 36 publications

(61 citation statements)

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“…8(b)), this will become an increasingly important trade-off when optimizing for higher values of X in radix-X. The effect of decreasing equivalent resistance can be partially mitigated by reducing the read voltage, where state-of-the-art crossbar arrays have demonstrated read currents of under 10nA [33].…”

Section: Discussionmentioning

confidence: 99%

“…To achieve analog or multi-bit states, the width of the filament must be precisely modulated, which is challenging in practice. It often requires the use of lower write voltages applied across longer durations, which super-exponentially increase the time of write cycles [33]. Therefore, many realizations of crossbar arrays employ conservative design techniques and treat metal-oxide memory cells as single-bit storage [34].…”

Section: A Resistive Switching In Memristorsmentioning

confidence: 99%

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Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars

Lee¹,

Eshraghian²,

Cho³

et al. 2019

Preprint

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Neural processor development is reducing our reliance on remote server access to process deep learning operations in an increasingly edge-driven world. By employing inmemory processing, parallelization techniques, and algorithmhardware co-design, memristor crossbar arrays are known to efficiently compute large scale matrix-vector multiplications. However, state-of-the-art implementations of negative weights require duplicative column wires, and high precision weights using single-bit memristors further distributes computations. These constraints dramatically increase chip area and resistive losses, which lead to increased power consumption and reduced accuracy. In this paper, we develop an adaptive precision method by varying the number of memristors at each crosspoint. We also present a weight mapping algorithm designed for implementation on our crossbar array. This novel algorithm-hardware solution is described as the radix-X Convolutional Neural Network Crossbar Array, and demonstrate how to efficiently represent negative weights using a single column line, rather than double the number of additional columns. Using both simulation and experimental results, we verify that our radix-5 CNN array achieves a validation accuracy of 90.5% on the CIFAR-10 dataset, a 4.5% improvement over binarized neural networks whilst simultaneously reducing crossbar area by 46% over conventional arrays by removing the need for duplicate columns to represent signed weights.Index Terms-adaptive precision, algorithm hardware codesign, convolutional neural network (CNN), deep learning accelerator, low precision weight, memristor crossbar. I. INTRODUCTIONM ACHINE learning algorithms have become ubiquitous in the modern world, and are crucial in enabling computer systems which automatically update and improve with experience. This has opened up new frontiers in data analysis techniques. Deep learning refers to the use of a multilayered neural network where the sequence of layers between the input and output perform feature identification at various hierarchies, as inspired by an approximation of the neuronal connections within the brain [1]- [4]. A popular deep learning algorithm for structured data is the convolutional neural

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Section: Discussionmentioning

confidence: 99%

Section: A Resistive Switching In Memristorsmentioning

confidence: 99%

Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars

Lee¹,

Eshraghian²,

Cho³

et al. 2019

Preprint

View full text Add to dashboard Cite

show abstract

“…Memristors are now ubiquitous in neuromorphic computing literature due to their long retention [2]- [4], excellent scalability [5], [6], fast read and write speeds [7], [8], compatibility with CMOS technology [9]- [12], and precise weight updates [13], [14]. The development of dense integrated structures with 3-D stacked crossbar arrays enables an increase in the throughput for a given chip area, but thus far, target applications of 3-D RRAM have mostly been limited to digital memory [16]- [23].…”

Section: Introductionmentioning

confidence: 99%

A 3-D Reconfigurable RRAM Crossbar Inference Engine

Eshraghian

Cho

Kang

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Deep neural network inference accelerators are rapidly growing in importance as we turn to massively parallelized processing beyond GPUs and ASICs. The dominant operation in feedforward inference is the multiply-and-accumlate process, where each column in a crossbar generates the current response of a single neuron. As a result, memristor crossbar arrays parallelize inference and image processing tasks very efficiently. In this brief, we present a 3-D active memristor crossbar array 'CrossStack', which adopts stacked pairs of Al/TiO 2/TiO2 -x/Al devices with common middle electrodes. By designing CMOS-memristor hybrid cells used in the layout of the array, CrossStack can operate in one of two user-configurable modes as a reconfigurable inference engine: 1) expansion mode and 2) deep-net mode. In expansion mode, the resolution of the network is doubled by increasing the number of inputs for a given chip area, reducing IR drop by 22%. In deep-net mode, inference speed per-10-bit convolution is improved by 29% by simultaneously using one TiO 2/TiO2 -x layer for read processes, and the other for write processes. We experimentally verify both modes on our 10 × 10 × 2 array.Index Terms-deep learning, in-memory computing, memristors, neural network, RRAM.

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“…Two-dimensional (2D) materials with atomic thickness and flatness have shown great potential for numerous applications in electronics (14)(15)(16)(17) and optoelectronics (18)(19)(20). The vdW vertical heterostructures formed by stacking different 2D materials accommodate an abundance of electronic and optoelectronic properties (21)(22)(23)(24)(25)(26)(27)(28)(29)(30)(31)(32), which may be exploited to mimic hierarchical architecture and functions of retinal neurons (33)(34)(35)(36)(37)(38)(39)(40)(41)(42)(43) in a natural manner to implement a neural network vision sensor.…”

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confidence: 99%

Gate-tunable van der Waals heterostructure for reconfigurable neural network vision sensor

et al. 2020

Self Cite

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Early processing of visual information takes place in the human retina. Mimicking neurobiological structures and functionalities of the retina provides a promising pathway to achieving vision sensor with highly efficient image processing. Here, we demonstrate a prototype vision sensor that operates via the gate-tunable positive and negative photoresponses of the van der Waals (vdW) vertical heterostructures. The sensor emulates not only the neurobiological functionalities of bipolar cells and photoreceptors but also the unique connectivity between bipolar cells and photoreceptors. By tuning gate voltage for each pixel, we achieve reconfigurable vision sensor for simultaneous image sensing and processing. Furthermore, our prototype vision sensor itself can be trained to classify the input images by updating the gate voltages applied individually to each pixel in the sensor. Our work indicates that vdW vertical heterostructures offer a promising platform for the development of neural network vision sensor.

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Parallel Programming of an Ionic Floating-Gate Memory Array for Scalable Neuromorphic Computing

Cited by 36 publications

References 0 publications

Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars

Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars

A 3-D Reconfigurable RRAM Crossbar Inference Engine

Gate-tunable van der Waals heterostructure for reconfigurable neural network vision sensor

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