Parallel Processing with the Perfect Shuffle

Stone, Harold S.

doi:10.1109/t-c.1971.223205

Cited by 1,100 publications

(212 citation statements)

References 7 publications

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“…If π 1 and π 2 are one-unit cyclic shifts, they can simulate data movement on a shuffle exchange graph. This in turn can be used to simulate a butterfly graph, which allows for arbitrary data permutations [16].…”

Section: Codeword Permutationsmentioning

confidence: 99%

A framework for coded computation

Rachlin

Savage

2008

2008 IEEE International Symposium on Information Theory

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Abstract-Error-correcting codes have been very successful in protecting against errors in data transmission. Computing on encoded data, however, has proved more difficult. In this paper we extend a framework introduced by Spielman [14] for computing on encoded data. This new formulation offers significantly more design flexibility, reduced overhead, and simplicity. It allows for a larger variety of codes to be used in computation and makes explicit conditions on codes that are compatible with computation. We also provide a lower bound on the overhead required for a single step of coded computation.

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Section: Codeword Permutationsmentioning

confidence: 99%

A framework for coded computation

Rachlin

Savage

2008

2008 IEEE International Symposium on Information Theory

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“…An (N×N) switch consists of n = log 2 N stages and N unbuffered (3×3) SEs per stage. Successive stages are interconnected through the perfect shuffle pattern [St71]. All the SEs in a particular row are linked to a corresponding input and output of the switch.…”

Section: Folded Shuffle Switchmentioning

confidence: 99%

The Folded Hypercube ATM Switches

Park

Davis

2001

Networking — ICN 2001

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Over the past few years, many high performance asynchronous transfer mode (ATM) switches have been proposed. The majority of these switches have high performance but also high hardware complexity. Therefore, there is a need for switch designs with low complexity and high performance. This research proposes three new ATM switches based on the folded hypercube network (FHC). The performance of the three architectures are studied using a network model and simulation. The major performance parameters measured are the cell loss rate and cell delay time through the switch under uniform, normal, and bursty traffic patterns. To guarantee faster switching of time-sensitive cells, the routing algorithm of the three switches uses a priority scheme that gives higher precedence to the time-sensitive cells. Also, an output buffer controller is designed to manage the buffers in a fair manner. The three proposed switch architectures have lower complexity while providing equivalent or better switching performance compared to other more complex ATM switches described in the literature. This research shows a new approach to designing ATM switches by using the FHC as the switching fabric for the first time instead of using the crossbar, multi-path, or Banyan-based switching fabrics.iii DedicationsAfter a long and painful fight against cancer, my grandfather passed away on Christmas Eve, 1999.He deeply wanted to, but was not able to see me receive the doctorate degree. I was blessed to receive his continual love and support for me. I hope he is looking down on me from heaven feeling proud.This dissertation is dedicated to my grandfather, Wookyu Park, in his loving memory.

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“…To efficiently process FFT, a number of hardware architectures have been proposed, including serial processing on a single processor [2], pipelined processing [7]- [10], and parallel processing [3]- [6]. Among them, the pipelined processing is preferred, as it can provide a high performance with a moderate hardware cost.…”

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confidence: 99%

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

Lee

Park

2007

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents an area-efficient algorithm for the pipelined processing of fast Fourier transform (FFT). The proposed algorithm is to decompose a discrete Fourier transform (DFT) into two balanced sub-DFTs in order to minimize the total number of twiddle factors to be stored into tables. The radix in the proposed decomposition is adaptively changed according to the remaining transform length to make the transform lengths of sub-DFTs resulting from the decomposition as close as possible. An 8192-point pipelined FFT processor designed for digital video broadcasting-terrestrial (DVB-T) systems saves 33% of general multipliers and 23% of the total size of twiddle factor tables compared to a conventional pipelined FFT processor based on the radix-2 2 algorithm. In addition to the decomposition, several implementation techniques are proposed to reduce area, such as a simple index generator of twiddle factor and add/subtract units combined with the two's complement operation.Index Terms-Balanced binary-tree decomposition, digital video broadcasting-terrestrial (DVB-T), fast Fourier transform (FFT), orthogonal frequency division multiplexing (OFDM), pipelined processing.

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Parallel Processing with the Perfect Shuffle

Cited by 1,100 publications

References 7 publications

A framework for coded computation

A framework for coded computation

The Folded Hypercube ATM Switches

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

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