Parallel multi-layer selector S-Box based on lorenz chaotic system with FPGA implementation

Saber, Mohamed; Hagras, Esam A. A.

doi:10.11591/ijeecs.v19.i2.pp784-792

Cited by 5 publications

(4 citation statements)

References 21 publications

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“…Table 3 presents a comparative analysis of the current study and previous research conducted in the field of integrated chaos. It is evident from Table 3 that the study conducted by [ 35 , 43 ] presents chaotic circuits constructed using discrete devices. However, it is important to note that the performance of these circuits is not comparable to that of an integrated chaotic circuit in various aspects.…”

Section: Chaotic Chip Layout and Its Simulationsmentioning

confidence: 99%

Integrated Circuit of a Chua’s System Based on the Integral-Differential Nonlinear Resistance with Multi-Path Voltage-Controlled Oscillator

Duan,

Li,

et al. 2024

Micromachines

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In this paper, we present a fully integrated circuit without inductance implementing Chua’s chaotic system. The circuit described in this study utilizes the SMIC 180 nm CMOS process and incorporates a multi-path voltage-controlled oscillator (VCO). The integral-differential nonlinear resistance is utilized as a variable impedance component in the circuit, constructed using discrete devices from a microelectronics standpoint. Meanwhile, the utilization of a multi-path voltage-controlled oscillator ensures the provision of an adequate oscillation frequency and a stable waveform for the chaotic circuit. The analysis focuses on the intricate and dynamic behaviors exhibited by the chaotic microelectronic circuit. The experimental findings indicate that the oscillation frequency of the VCO can be adjusted within a range of 198 MHz to 320 MHz by manipulating the applied voltage from 0 V to 1.8 V. The circuit operates within a 1.8 V environment, and exhibits power consumption, gain–bandwidth product (GBW), area, and Lyapunov exponent values of 1.0782 mW, 4.43 GHz, 0.0165 mm2, and 0.6435∼1.0012, respectively. The aforementioned circuit design demonstrates the ability to generate chaotic behavior while also possessing the benefits of low power consumption, high frequency, and a compact size.

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Section: Chaotic Chip Layout and Its Simulationsmentioning

confidence: 99%

Integrated Circuit of a Chua’s System Based on the Integral-Differential Nonlinear Resistance with Multi-Path Voltage-Controlled Oscillator

Duan,

Li,

et al. 2024

Micromachines

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“…Saber et al developed a high‐speed FPGA implementation of parallel multilayer S‐Boxes based on the Lorenz chaotic system (PMLS S‐Box). The proposed PMLS chaotic S‐Box is modeled in a 32‐bit fixed‐point format using Xilinx System Generator (XSG), and the architecture is applied to the Xilinx Spartan‐6 X6SLX45 board 17 . Campos‐Cantón et al proposed a work on the electronic application of tent map.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed PMLS chaotic S-Box is modeled in a 32-bit fixed-point format using Xilinx System Generator (XSG), and the architecture is applied to the Xilinx Spartan-6 X6SLX45 board. 17 Campos-Cant on et al proposed a work on the electronic application of tent map. For this circuit, integrated circuits and passive elements are used.…”

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confidence: 99%

FPGA simulation of chaotic tent map‐based S‐Box design

Türk

2022

Circuit Theory & Apps

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The chaotic system has a characteristically random behavior by nature, and these systems have their own characteristics in a completely deterministic structure. This feature of a chaotic system makes it difficult to predict encryptions designed based on such a system. Thanks to this unpredictable and strong feature, maps produced from chaotic systems are an important alternative in the field of encryption. One of the structures obtained by employing chaotic maps is the substitution box. S‐Box, which provides the confusion principle used in block ciphers, is the main block that dynamically replaces unencrypted data with confidential data and makes a significant contribution to ensuring high security in the encryption system. Therefore, S‐Boxes hold a critical role in block ciphers. Speed and reliability are important parameters in the creation of this main block. Especially, applications performed on hardware are more reliable and high performance. Therefore, in this study, an S‐Box was designed using field‐programmable gate arrays (FPGA) simulation from a chaotic tent map to create a fast and reliable S‐Box because FPGAs offer solutions that may be important in this field considering their fast and customizable architecture. In the proposed method, the S‐Box was created in 0.16 s. In addition, the dynamic properties of the chaotic tent map were analyzed with Lyapunov exponents, and the NIST SP 800‐22 test was applied for the information encryption suitability of the proposed chaotic system. Also, to test the reliability of the produced S‐Box structures, SAC, non‐linearity, bit independence criteria, and input/output XOR distribution table metrics were implemented. The results showed that the proposed chaotic map was dynamic and passed the reliability tests successfully.

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“…The S-box performs a nonlinear operation in cryptography. Also several studies were carried out for S-box constitution from chaotic system by using FPGA Parallel Multi-Layer Selector Substitution Boxes based on the Lorenz Chaotic System and its FPGA implementation were carried out [11]. Speech encryption using a chaotic system and an S-box table on FPGA was studied [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Cosimulation of S-Box Constitution from Fractional Order Liu System

Ali

Türk

2022

Preprint

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Substitution box(S-box) has an important duty in encryption. In recent years plenty of S-box designs by chaotic systems have been studied. In this paper a high speed S-box constitution from fractional order Liu system on FPGA is proposed. The design was implemented by using Xilinx System Generator(XSG) toolbox in MATLAB/Simulink software in single precision floating point numbers format and a low cost Basys 3 FPGA trainer card was used. In addition, numerical fractional order equations was solved by using Grünwald-Letnikov(GL) method with 1024 elements length. The S-box table was constructed about 0.137s. After all performance analyzes as nonlinearity, strict avalanche criterion, differential probability, bits independent criterion, and equiprobable input/output XOR distribution, were performed. The performance analyzes shown that the design was satisfactory.

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Parallel multi-layer selector S-Box based on lorenz chaotic system with FPGA implementation

Cited by 5 publications

References 21 publications

Integrated Circuit of a Chua’s System Based on the Integral-Differential Nonlinear Resistance with Multi-Path Voltage-Controlled Oscillator

Integrated Circuit of a Chua’s System Based on the Integral-Differential Nonlinear Resistance with Multi-Path Voltage-Controlled Oscillator

FPGA simulation of chaotic tent map‐based S‐Box design

FPGA-Based Cosimulation of S-Box Constitution from Fractional Order Liu System

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