Parallel matrix multiplication on memristor-based computation-in-memory architecture

Haron, Adib; Yu, Jintao; Nane, Răzvan; Taouil, Mottaqiallah; Hamdioui, Said; Bertels, Koen

doi:10.1109/hpcsim.2016.7568411

Cited by 19 publications

(11 citation statements)

References 28 publications

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“…Memristor [4], [5]-based Computation-in-Memory (CIM) architectures [6]- [9] address the aforementioned problems by enabling in-memory processing using emerging nonvolatile technologies. Manually designed case studies revealed their enormous potential by outperforming the state-of-the-art with orders of magnitude [10]- [12]. Exploring the potential of such architectures and appropriately evaluating their performance and scalability for larger applications require automatic flows and methods that efficiently map high-level algorithmic description to low-level memristor crossbar configuration.…”

Section: Introductionmentioning

confidence: 99%

Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures

Nane

Ashraf

et al. 2020

IEEE Trans. Emerg. Topics Comput.

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Memristor-based Computation-in-Memory (CIM) is one of the emerging architectures for next-generation Big Data problems. Its design requires a radically new synthesis flow because the memristor is a passive device that uses resistance to encode its logic value. This article proposes a synthesis flow for mapping parallel applications on memristor-based CIM architecture. It employs solution templates that contain scheduling, placement, and routing information to map multiple algorithms with similar data flow graphs to memristor crossbar; this template is named skeleton. Complex algorithms that do not fit any skeleton can be solved by nested skeletons. Therefore, this approach can be applied to a wide range of applications with a limited number of skeletons. It further improves the design when spatial and temporal patterns exist in input data. To accelerate simulation of generated SystemC models, we integrate MPI in skeletons. The synthesis flow and its additional features are verified with multiple applications, and the results are compared against a multicore platform. These experiments demonstrate the feasibility and the potential of this approach.

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Section: Introductionmentioning

confidence: 99%

Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures

Nane

Ashraf

et al. 2020

IEEE Trans. Emerg. Topics Comput.

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“…Among these proposals, memristor crossbar based logic circuit is a promising candidate due to its attractive characteristics in terms of scalability, high integration density, and non-volatility, etc [15,16]. Moreover, based on memristor technology, novel computer architectures for data-intensive applications have been proposed, such as computation-in-memory [17][18][19][20][21], resistive associate processor [22] and Pinatubo [23]; they show a potential of order of magnitude performance improvement as compared to todays' architectures.…”

Section: Introductionmentioning

confidence: 99%

A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

Xie

Nguyen

Taouil

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Alternatives to CMOS logic circuit implementations are under research for future scaled electronics. Memristor crossbar based logic circuit is one of the promising candidates to at least partially replace CMOS technology, which is facing many challenges such as reduced scalability, reliability, and performance gain. Memristor crossbar offers many advantages including scalability, high integration density, non-volatility, etc. The state-of-the-art for memristor crossbar logic circuit design can only implement simple and small circuits. This paper proposes a mapping methodology of large Boolean logic circuits on memristor crossbar. Appropriate place-and-route schemes, to efficiently map the circuits on the crossbar, as well as several optimization schemes are also proposed. To illustrate the potential of the methodology, a multi-bit adder and other nine more complex benchmarks are studied; the delay, area and power consumption induced by both the crossbar and its CMOS control part are evaluated.

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“…One utilizes two or more reference cells to distinguish the different resistance states 55 of the data cells participating in the logic operations, while the other one executes the logic operations by its complementary structure [5,21,22]. Most of the CIM paradigms have been presented and assessed at architecture level [6,[23][24][25]. They 60 are based on the idea of adding necessary peripheral circuits to the memory, which makes the memory has some kinds of computation capability and storage capability at the same time [26][27][28].…”

Section: Introductionmentioning

confidence: 99%

A high-reliability and low-power computing-in-memory implementation within STT-MRAM

Zhang

Deng

Cai

et al. 2018

Microelectronics Journal

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et al.. A high-reliability and low-power computing-in-memory implementation within STT-MRAM. Microelectronics Journal, Elsevier, 2018, 81, pp. AbstractIn the conventional Von-Neumann computer architecture, more energy and time are consumed by the data transport, rather than the computation itself because of the limited bandwidth between the processor and memory. Computing-in-memory (CIM) is therefore proposed to effectively address the issue by moving some specified kinds of computation into the memory. It has been proposed for several decades, however, not really used when considering the reliability and cost. With the emergence of non-volatile memories, the CIM has regained interest to tackle the issue. In this paper, we implement a CIM scheme: ComRef (Complementary Reference) within STT-MRAM (Spin Transfer Torque Magnetic Random-Access Memory), and then compare its reliability and performance with the DualRef (Dual Reference) CIM implementation. Simulation results reveal that the ComRef obviously improves the reliability by decreasing 67.1% of the operation error rate and by increasing up to 57.4% of the sensing margin. It accelerates the bitwise logic operation with cutting down 20.8% (∼41.1 ps) of the operation delay. Most importantly, it is highly energy efficient by reducing 23.4% of the average dynamic energy and 65.6% of the average static power. The ComRef provides a pathway to implement high-reliability and low-power CIM paradigm within STT-MRAM. the measurement in [4], about 200 times more energy is dissipated to access DRAM one time when compared with a floating-point computation. In summary, the limited bandwidth between the processor and the memory has been one of the most 20 critical bottlenecks to improve the system performance. This is the well-known processor-memory gap or "memory wall" [5].To address the issue, the closer integration of logic and memory has been explored widely, such as 25 logic-in-memory, processing-in-memory, in-memory processing. These explorations can be classified as two types: 1) near memory computing, 2) executing some specified kinds of computations within memory, it is called computing-in-memory (CIM). The 30CIM can reduce the amount of data transferring between the processors and the memory, to mitigate the stress of data transport on the limited bandwidth [6,7]. However, the CIM fails to tackle the issue due to some practical considerations. In 35

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Parallel matrix multiplication on memristor-based computation-in-memory architecture

Cited by 19 publications

References 28 publications

Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures

Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures

A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

A high-reliability and low-power computing-in-memory implementation within STT-MRAM

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