2018 IEEE International Symposium on Circuits and Systems (ISCAS) 2018
DOI: 10.1109/iscas.2018.8350924
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Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

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“…However, recent work has demonstrated data converters operating at sampling rates up to 90 GS/s with a resolution of 8 bits or higher [13], [14]. Moreover, the DSP required for DMT has been implemented with low power consumption [15]. Therefore, there is a renewed interest in examining the potential of DMT for high-speed wireline communication, with a recent example [16] reporting a receiver energy efficiency of 2.9 pJ/b at 56 Gb/s.…”
Section: Introductionmentioning
confidence: 99%
“…However, recent work has demonstrated data converters operating at sampling rates up to 90 GS/s with a resolution of 8 bits or higher [13], [14]. Moreover, the DSP required for DMT has been implemented with low power consumption [15]. Therefore, there is a renewed interest in examining the potential of DMT for high-speed wireline communication, with a recent example [16] reporting a receiver energy efficiency of 2.9 pJ/b at 56 Gb/s.…”
Section: Introductionmentioning
confidence: 99%