Parallel image restoration using surrogate constraint methods

2010

Information Sciences

Self Cite

Get-Successors (GS) which retrieves all successors of a junction is a kernel operation used to facilitate aggregate computations in road network queries. Efficient implementation of the GS operation is crucial since the disk access cost of this operation constitutes a considerable portion of the total query processing cost. Firstly, we propose a new successor retrieval operation Get-Unevaluated-Successors (GUS), which retrieves only the unevaluated successors of a given junction. The GUS operation is an efficient implementation of the GS operation, where the candidate successors to be retrieved are pruned according to the properties and state of the algorithm. Secondly, we propose a hypergraph-based model for clustering successively retrieved junctions by the GUS operations to the same pages. The proposed model utilizes query logs to correctly capture the disk access cost of GUS operations. The proposed GUS operation and associated clustering model are evaluated for two different instances of GUS operations which typically arise in Dijkstra's single source shortest path algorithm and incremental network expansion framework. Our simulation results show that the proposed successor retrieval operation together with the proposed clustering hypergraph model is quite effective in reducing the number of disk accesses in query processing. © 2010 Published by Elsevier Inc

Section: Graph and Hypergraph Partitioningmentioning

confidence: 99%

Efficient successor retrieval operations for aggregate query processing on clustered road networks

Demir

2010

Information Sciences

Self Cite

“…In these models, the partitioning objective is to minimize the total volume of communication while maintaining the computational load balance. These matrix partitioning models are used in different applications that involve repeated matrix-vector multiplies, such as computa-tion of response time densities in large Markov models [26], restoration of blurred images [52], and integer factorization in the number field sieve algorithm in cryptology [7].…”

Section: Applications Of Hypergraph Partitioningmentioning

confidence: 99%

Multi-level direct K-way hypergraph partitioning with multiple constraints and fixed vertices

Journal of Parallel and Distributed Computing

Cambazoğlu

Uçar

2008

Self Cite

100

K-way hypergraph partitioning has an ever-growing use in parallelization of scientific computing applications. We claim that hypergraph partitioning with multiple constraints and fixed vertices should be implemented using direct K-way refinement, instead of the widely adopted recursive bisection paradigm. Our arguments are based on the fact that recursive-bisection-based partitioning algorithms perform considerably worse when used in the multiple constraint and fixed vertex formulations. We discuss possible reasons for this performance degradation. We describe a careful implementation of a multi-level direct K-way hypergraph partitioning algorithm, which performs better than a well-known recursive-bisection-based partitioning algorithm in hypergraph partitioning with multiple constraints and fixed vertices. We also experimentally show that the proposed algorithm is effective in standard hypergraph partitioning.

“…Typical examples include iterative methods for solving linear programming (LP) problems through interior point methods [1], [2]; the Biconjugate Gradient (BCG), the Conjugate Gradient for the Normal Equations (CGNE), the Conjugate Gradient for the Normal Residual (CGNR), and the Lanczos Biorthogonalization methods [3] for solving nonsymmetric linear systems; the LSQR method [4] for solving the least squares problem; the Surrogate Constraints method [5], [6] for solving the linear feasibility problem; the Hyperlink-Induced Topic Search (HITS) algorithm [7], [8] for rating web pages; and the Krylov-based balancing algorithms [9] used as preconditioners for sparse eigensolvers.…”

Section: Introductionmentioning

confidence: 99%

Locality-Aware Parallel Sparse Matrix-Vector and Matrix-Transpose-Vector Multiplication on Many-Core Processors

Karsavuran

Akbudak

IEEE Trans. Parallel Distrib. Syst.

2016

Self Cite

Sparse matrix-vector and matrix-transpose-vector multiplication (SpMM T V) repeatedly performed as z A T x and y A z (or y A w) for the same sparse matrix A is a kernel operation widely used in various iterative solvers. One important optimization for serial SpMM T V is reusing A-matrix nonzeros, which halves the memory bandwidth requirement. However, thread-level parallelization of SpMM T V that reuses A-matrix nonzeros necessitates concurrent writes to the same output-vector entries. These concurrent writes can be handled in two ways: via atomic updates or thread-local temporary output vectors that will undergo a reduction operation, both of which are not efficient or scalable on processors with many cores and complicated cache-coherency protocols. In this work, we identify five quality criteria for efficient and scalable thread-level parallelization of SpMM T V that utilizes one-dimensional (1D) matrix partitioning. We also propose two locality-aware 1D partitioning methods, which achieve reusing A-matrix nonzeros and intermediate z-vector entries; exploiting locality in accessing x-, y-, and z-vector entries; and reducing the number of concurrent writes to the same output-vector entries. These two methods utilize rowwise and columnwise singly bordered block-diagonal (SB) forms of A. We evaluate the validity of our methods on a wide range of sparse matrices. Experiments on the 60-core cache-coherent Intel Xeon Phi processor show the validity of the identified quality criteria and the validity of the proposed methods in practice. The results also show that the performance improvement from reusing A-matrix nonzeros compensates for the overhead of concurrent writes through the proposed SB-based methods.Index Terms-Cache locality, sparse matrix, sparse matrix-vector multiplication, matrix reordering, singly bordered block-diagonal form, Intel Many Integrated Core Architecture (Intel MIC), Intel Xeon PhiThe authors are with the