Parallel FPGA-Based Implementation of Recursive Sorting Algorithms

Mihhailov, Dmitri; Sklyarov, Valery; Skliarova, Iouliia; Sudnitson, Alexander

doi:10.1109/reconfig.2010.30

Cited by 26 publications

(16 citation statements)

References 9 publications

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“…The tutorial suggests quicksort and radix sort to be combined with the proposed methods and circuits offering very good results. Different types of sorting over n-DU\ WUHHV Q ZHUH considered for sequential [30] and parallel [31] implementations. This method can be efficient if it is combined with the address-based technique [12].…”

Section: Other Methods For Data Processing In Fpgamentioning

confidence: 99%

Data processing in FPGA-based systems

Sklyarov

Skliarova

2012

2012 6th International Conference on Application of Information and Communication Technologies (AICT)

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More than 50% of FPGA market is in the scope of communication and information. Data processing is a very broad area that is important for numerous computations, networking, embedded systems, Internet-based applications, etc. Many problems in this area are computationally intensive and thus, they require parallelization and acceleration based on new technologies. FPGAs can be seen as a very attractive platform permitting application-specific software and problem-targeted hardware to be combined on a single configurable microchip. The tutorial is dedicated to hardware-oriented data processing algorithms with emphasis on parallelism and pipelining. FPGAtargeted design flow is based on the rational use of configurable logic blocks/logic elements and embedded components (DSP slices and block RAMs). Particular examples, potential practical applications, experiments and comparisons will be demonstrated.

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Section: Other Methods For Data Processing In Fpgamentioning

confidence: 99%

Data processing in FPGA-based systems

Sklyarov

Skliarova

2012

2012 6th International Conference on Application of Information and Communication Technologies (AICT)

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“…There are papers adopting reconfigurable architectures for sorting sequences [5], [6], [7], [8]. However, these architectures are typically expensive in terms of hardware resources.…”

Section: A Sorting-free Ordinal Pattern Encodingmentioning

confidence: 99%

“…For instance, the Lehmer code of the sequence x = (3,9,5,1,7,4,8) is L(x) = (1, 5, 2, 0, 1, 0, 0). One property of this encoding scheme is that one ordinal pattern uniquely maps to a Lehmer code.…”

Section: A Sorting-free Ordinal Pattern Encodingmentioning

confidence: 99%

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Pipelined reconfigurable accelerator for ordinal pattern encoding

Guo

Luk

Weston

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Ordinal analysis is a statistical method for analysing the complexity of time series. This method has been used in characterising dynamic changes in time series, with various applications such as financial risk modelling and biomedical signal processing. Ordinal pattern encoding is a fundamental calculation in ordinal analysis. It is computationally demanding particularly for high query orders and large time series data. This paper presents the first reconfigurable accelerator for this encoding calculation, with four main contributions. First, we propose a two-level hardware-oriented ordinal pattern encoding scheme to avoid sequence sorting operations in the accelerator, enabling theoretically best code compactness. Second, we develop a hardware mapping method by promoting data reuse, by parallelising arithmetic operations, and by pipelining the data path. Third, we conduct an experimental implementation of the proposed system, showing promising accelerated performance compared to software solutions. Finally, we apply the proposed accelerator to the computation of permutation entropy, demonstrating the significant potential for acceleration that would benefit such computation.

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“…Let us consider binary trees first [9,10]. Suppose each node of the tree contains three fields: a value (e.g.…”

Section: An Approach To Data Sortingmentioning

confidence: 99%

Performance evaluation for FPGA-based processing of tree-like structures

Sklyarov

Skliarova

Mihhailov

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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The paper evaluates tree-based implementations of data sorting algorithms in FPGA circuits using hierarchical finite state machine (HFSM) as a computational core. We focus here on experiments which show effectiveness of sorting algorithms over data structures represented in form of N-ary trees (N≥2). The presented results compare different types of data representation and processing in terms of performance and memory requirements. It is shown that using advanced FPGAs and the proposed address-based methods the number of sorted items with size 32-64 bits can reach 2 32 .

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Parallel FPGA-Based Implementation of Recursive Sorting Algorithms

Cited by 26 publications

References 9 publications

Data processing in FPGA-based systems

Data processing in FPGA-based systems

Pipelined reconfigurable accelerator for ordinal pattern encoding

Performance evaluation for FPGA-based processing of tree-like structures

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