Parallel field programmable gate array implementation of the sum of absolute differences algorithm used in the stereoscopic system

Abstract

Stereo vision is a popular method for an artificial vision-based environment perception system used in various applications such as intelligent transportation. With two cameras, the disparity map is calculated to find the distance and depth of objects in front of a moving vehicle. The key element of the stereoscopic system is based on the sum of absolute differences (SAD) algorithm, which is the most repeated operation in the stereo matching subsystem; however, this algorithm requires a very intensive processing time, statistical analysis show that the SAD block can consume more than 80% of the overall processing time of the algorithm. In this paper we propose a highly efficient hardware architecture of the SAD algorithm for real time stereo matching, the proposed architecture is established by a hierarchical parallel architecture of the SAD block, and verified by simulation and successfully implemented in Cyclone IV field programmable gate array (FPGA), it provides a significant reduction of processing time and the performance of the stereo imaging system is able to achieve 30 frames per second of 640×480 resolution color images.