Parallel external memory graph algorithms

Abstract

Abstract-In this paper, we study parallel I/O efficient graph algorithms in the Parallel External Memory (PEM) model, one of the private-cache chip multiprocessor (CMP) models. We study the fundamental problem of list ranking which leads to efficient solutions to problems on trees, such as computing lowest common ancestors, tree contraction and expression tree evaluation. We also study the problems of computing the connected and biconnected components of a graph, minimum spanning tree of a connected graph and ear decomposition of a biconnected graph. All our solutions on a P -processor PEM model provide an optimal speedup of Θ(P ) in parallel I/O complexity and parallel computation time, compared to the single-processor external memory counterparts.

Oblivious algorithms for multicores and networks of processors

“…Then, MO-IS incurs O((n/(q i B i )) log C i n + (C i /B i ) log p ′ i B 1 (q i C i ) log log n + log n(log log n) 2 ) misses. The upper bounds in the theorem follow by observing that the returned independent set has size n/3 [3], and thus the linked list shrinks to a size smaller than B 1 in O(log(n/B 1 )) applications of MO-IS.…”

“…respectively. This algorithm is derived from those in [3,15] by adopting our multicore-oblivious primitives for sorting and scanning and by recursively contracting the linked list down to a constant size, instead of a variable size based on architectural parameters. We use as sorting primitive the multicore-oblivious algorithm MO-MS given in Section 3.4.…”

“…By using the CGC hint, it is straightforward to obtain as in [32,3,15] multicore-oblivious algorithms for Euler tour, and several tree problems such as rooting a tree, traversal numbering, vertex depth, subtree size and connected components of a forest. These algorithms have the same complexity as MO-LR.…”

On (Dynamic) Range Minimum Queries in External Memory

“…The algorithm of Chiang et al [7] has been used by Arge et al [4] to develop a parallel solution to the static batched RMQ problem in the parallel external memory (PEM) model [3]. Our new linear space EM solution immediately leads to a linear space PEM solution.…”

Paging for multi-core shared caches

“…From a theoretical perspective, much attention has been given recently to schedulers and algorithms for multithreaded computations with provable cache performance, either for private caches [11,1,4,5,2], shared caches [9], both private and shared [10,16], or hierarchical cache configurations [8,17,40]. In these works the focus is on the design of either algorithms for specific problems or on general schedulers that yield cache performance guarantees.…”