Parallel CRC generation

Reunion: Complexity-Effective Multicore Redundancy

“…The total state updates per cycle can exceed 256 bits of state, which exceeds what parallel CRC circuits can consume in a single clock. We solve this problem by leveraging a two-stage compression technique used in circuit testing [7], which places space-compressing parity trees before a time-compressing circuit, such as a parallel CRC [2] or multiple-input shift register (MISR) [7]. Parity trees reduce the raw M bits of state down to N bits of compressed state in a single clock cycle, which then feed the time-compressing circuit in the next cycle.…”

Performance Increase of Error Control Operation on Data Transmission

“…The increase of speed for error control using the CRC method can be achieved by working with several bits simultaneously within the same block [2], [3]. However, the complexity of the matrix transformation, which realizes this approach, grows exponentially with the increase in the number of bits used simultaneously.…”

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

“…Fingerprinting [24] proposed the use of a CRC-16 compression circuit to compress all of the register file and memory updates each cycle. We simulated various parallel CRC circuits [2] in HSPICE and their fan-out-offour (FO4) delays 1 and transistors counts are shown in Table 1. Assuming a cycle time of 10-15 FO4s, a CRC-32 circuit and a CRC-16 circuit (2 stages) can compress up to 32 bits in one cycle.…”

“…2 (If all other processors are in use, the operating system must choose a core and switch-out its currently running thread.) To initiate this, the cache controller of the failing master core makes a TMR request by generating a special bus transaction that sets a flag in the kernel's address space.…”

“…Once the faulty processor is isolated, execution continues on the remaining two cores. 2 The involvement of the operating system in FER is unlikely to affect system performance since FER is only invoked on hard faults (a rare event) and in cases where the same checkpoint interval fails multiple times in a row due to soft errors (exceedingly unlikely). …”