Parallel contention resolution control for input queueing ATM switches

Obara, H.; Hamazumi, Y.

doi:10.1049/el:19920530

Cited by 10 publications

(5 citation statements)

References 2 publications

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“…In fact, HOL blocking can be eliminated entirely by using a simple buffering strategy at each input port. Rather than maintain a single FIFO queue for all cells, each input maintains a separate queue for each output [1] [9][15] [16][17] [18], as shown in Figure 1. This queueing discipline is often referred to as virtual output queueing.…”

Section: N Is Largementioning

confidence: 99%

Achieving 100% throughput in an input-queued switch

McKeown

Mekkittikul

Anantharam

et al. 1999

IEEE Trans. Commun.

683

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-It is well known that head-of-line (HOL) blocking limits the throughput of an input-queued switch with FIFO queues. Under certain conditions, the throughput can be shown to be limited to approximately 58%. It is also known that if non-FIFO queueing policies are used, the throughput can be increased. However, it has not been previously shown that if a suitable queueing policy and scheduling algorithm are used then it is possible to achieve 100% throughput for all independent arrival processes. In this paper we prove this to be the case using a simple linear programming argument and quadratic Lyapunov function. In particular, we assume that each input maintains a separate FIFO queue for each output and that the switch is scheduled using a maximum weight bipartite matching algorithm. We introduce two maximum weight matching algorithms: LQF and OCF. Both algorithms achieve 100% throughput for all independent arrival processes. LQF favors queues with larger occupancy, ensuring that larger queues will eventually be served. However, we find that LQF can lead to the permanent starvation of short queues. OCF overcomes this limitation by favoring cells with large waiting times.

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Section: N Is Largementioning

confidence: 99%

Achieving 100% throughput in an input-queued switch

McKeown

Mekkittikul

Anantharam

et al. 1999

IEEE Trans. Commun.

683

View full text Add to dashboard Cite

show abstract

“…In fact, HOL blocking can be eliminated entirely by using a simple buffering strategy at each input port. Rather than maintain a single FIFO queue for all cells, each input maintains a separate queue for each output [1][9] [15] [16][17] [18], as shown in Figure 1. HOL blocking is eliminated because a cell cannot be held up by a cell queued ahead of it that is destined for a different output.…”

Section: N Is Largementioning

confidence: 99%

Achieving 100% throughput in an input-queued switch

McKeown

Anantharam

Walrand

Proceedings of IEEE INFOCOM '96. Conference on Computer Communications

656

700

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“…In this case a later cell destined for a di erent output can be blocked by the HOL cell if the HOL cell is destined for an output that is already receiving a cell from a di erent input. Many scheduling algorithms have been propose that maintain separate virtual queues for each output at each input by permitting the server to access all bu er positions, not just the rst 3,15,22,23,24,25,26]. Simulations have shown that such heuristic algorithms perform well when tra c is independent and uniform, but they do not perform as well for nonuniform tra c 22,23].…”

Section: Introductionmentioning

confidence: 99%

Scheduling of an Input-Queued Switch to Achieve Maximal Throughput

Altman

Liu

Righter

2000

Prob. Eng. Inf. Sci.

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Achieving high throughput in input-queued switches has been found to be difficult, especially when traffic is nonuniform in the sense that different inputs have very different cell generation rates. We show that for general arrival processes, 100% throughput can be achieved with a simple algorithm that is very easy to implement.We consider a switch in which in each time slot, at most one cell may be transmitted from each input, and at most one cell may be received at each output. Cells that are destined for output j arrive at input i according to a stationary and ergodic process, and arrivals are queued at the input. The problem is to decide which inputs are to transmit to which outputs in each time slot in order to maximize throughput. Necessary conditions for stability are that the total arrival rate to each input must be less than 1, and the total arrival rate destined to each output must be less than 1. We propose a simple scheduling algorithm and show that with this algorithm the necessary conditions for stability are also sufficient.

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Parallel contention resolution control for input queueing ATM switches

Cited by 10 publications

References 2 publications

Achieving 100% throughput in an input-queued switch

Achieving 100% throughput in an input-queued switch

Achieving 100% throughput in an input-queued switch

Scheduling of an Input-Queued Switch to Achieve Maximal Throughput

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