Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput

Tran, Dat Q.; Aslam, Shahid; Gorius, N.; Nehmetallah, George

doi:10.3390/electronics10070866

Cited by 5 publications

(3 citation statements)

References 14 publications

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“…In future designs, we consider that the error detection and correction in node communication links is a key consideration that ensures the system robustness in practical applications. Specifically, we might incorporate bit level error detection and correction methods like Cyclic Redundancy Checksum (CRC) [56][57][58] and MD5…”

Section: Discussionmentioning

confidence: 99%

Butterfly: μW Level ULP Sensor Nodes with High Task Throughput

Zhang¹,

Lu²,

Song³

et al. 2022

Sensors

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The rapid development of Internet of Things (IoT) applications calls for light-weight IoT sensor nodes with both low-power consumption and excellent task execution efficiency. However, in the existing system framework, designers must make trade-offs between these two. In this paper, we propose an “edge-to-end integration” design paradigm, Butterfly, which assists sensor nodes to perform sensing tasks more efficiently with lower power consumption through their (high-performance) network infrastructures (i.e., a gateway). On the one hand, to optimize the power consumption, Butterfly offloads the energy-intensive computational tasks from the nodes to the gateway with only microwatt-level power budget, thereby eliminating the power-consuming Microcontroller (MCU) from the node. On the other hand, we address three issues facing the optimization of task execution efficiency. To start with, we buffer the frequently used instructions and data to minimize the volume of data transmitted on the downlink. Furthermore, based on our investigation on typical sensing data structures, we present a novel last-bit transmission and packaging mechanism to reduce the data amount on the uplink. Finally, we design a task prediction mechanism on the gateway to support efficient scheduling of concurrent tasks on multiple MCU-free Butterfly nodes. The experiment results show that Butterfly can speed up the task rate by 4.91 times and reduce the power consumption of each node by 94.3%, compared to the benchmarks. In addition, Butterfly nodes have natural security advantages (e.g., anti-capture) as they offload the control function with all application information up to the gateway.

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Section: Discussionmentioning

confidence: 99%

Butterfly: μW Level ULP Sensor Nodes with High Task Throughput

Zhang¹,

Lu²,

Song³

et al. 2022

Sensors

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show abstract

“…As already mentioned, in 100 Gbps OLANs, the data is protected by CRC or RS codes. Although these codes can be encoded/decoded in linear [14] and quasi‐log‐linear time [15], respectively, they are not suitable for software implementation. The reason is that they use finite field arithmetic, which is not supported by general purpose processors (GPPs).…”

Section: Evaluation and Implementation Strategymentioning

confidence: 99%

Integer codes correcting single errors and detecting burst errors within two bytes

2023

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The need for fast communication has led to the introduction of 100 Gbps optics in local area networks (LANs). To avoid retransmission of corrupted packets, in some LANs, the CRC codes were replaced by Reed‐Solomon (RS) codes. Although this solution has met its primary goal, it has two drawbacks: first, the payload size was significantly reduced, and second, each network node had to be equipped with much more complex hardware, which increased the cost of the network. Starting from the fact that the vast majority of corrupted packets contain only single errors, in this paper, a simple strategy for error control in 100 Gbps optical LANs is presented. More precisely, instead of protecting the data with the CRC or RS codes, using integer codes is suggested that can correct single errors and detect two types of burst errors: l‐bit burst errors within one b‐bit byte and h‐bit burst errors within two b‐bit bytes (1 ≤ h < l < b). Unlike the CRC or RS codes, the proposed ones use integer and lookup table operations, which are supported by all processors. In addition, the proposed codes can be interleaved without delay and without using any additional hardware. This feature allows the decoder not only to process larger data sets in parallel, but also to detect all double burst errors.

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“…The gains of parallel computing systems have been exploited by researchers in other fields as well: In bioinformatics; parallel programming technology was employed for genome sequence processing in [25]. In electronics, a parallel computation method to curb the bottleneck incurred by serial computation of CRC was exploited in [26]. The method efficiently increased speed-up in the computation of (cyclic redundancy check) CRC computation on CPU and Field Programmable Gate Array (FPGA).…”

Section: Parallelism and Multicoresmentioning

confidence: 99%

Enhancing Parallel Scheduling of Grid Jobs in a Multicored Environment

Abraham¹,

Osaisai²,

Ineyekineye³

2021

MCS

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The computing Grid has emerged as a platform to solve the complex and ever-increasing processing need of man and advances in computing technology have birthed the multicore era aimed for high throughput and efficient parallel computing. However, most systems still rely on the underlying hardware for parallelism despite the hard evidence that sequential algorithms do not optimally exploit parallel systems. This research seeks to harness the benefits of multicore systems using job and machine grouping methods to enhance parallelism in the scheduling of Grid jobs. The paper presents the result of two separate experiments on a method that parallelize scheduling algorithm on two multicore platforms. An arbitrary method was employed to group machines; a summation of the total processing power of machines in each group was made. To ensure load balancing, jobs were allocated to machine groups based on the ratio of the total processing power of the machines in each group. The MinMin Grid scheduling algorithm was implemented independently within the groups using a range of threads varied in powers of two. Also, the numbers of groups were varied between 2, 4, and 8. The same experiment was executed on a single processor computer; a duocore machine and a quadcore machine. A performance improvement of 16% to 85% was recorded by the group method against the best ordinary MinMin results and an improvement of 50% to 84% was recorded by the group method against the ordinary MinMin on corresponding machines. We prove that an increase in the number of groups results in improved performance on corresponding machines (approximately 2 times using 2 groups, approximately 3 times using four groups, and approximately 6 times using 8 groups). And most importantly, we established that as the number of processors increases, the grouping method makes more significant improvements over the ordinary MinMin scheduling algorithm executed on the multicore systems.

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Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput

Cited by 5 publications

References 14 publications

Butterfly: μW Level ULP Sensor Nodes with High Task Throughput

Butterfly: μW Level ULP Sensor Nodes with High Task Throughput

Integer codes correcting single errors and detecting burst errors within two bytes

Enhancing Parallel Scheduling of Grid Jobs in a Multicored Environment

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