Parallel Algorithms for VLSI Layout Verification

Macpherson, K.N.; Banerjee, P.

doi:10.1006/jpdc.1996.0096

Cited by 9 publications

(2 citation statements)

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“…The main limiting factor in these cases is dealing with geometry operations that need connectivity information for correct output and how this information is handled across partitions. A previous paper [5] presented a parallel design rule checking framework that can handle data parallelism but it does not present any clear solutions for dealing with connectivity information across partitions. There has been some work on data-parallel DRC solutions for specific machine architectures [4].…”

Section: Introductionmentioning

confidence: 98%

A distributed algorithm for layout geometry operations

Hsu

Sinha

et al. 2011

Proceedings of the 48th Design Automation Conference

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This paper introduces a novel distributed algorithm for performing layout geometry operations usually found in design rule checking, layout verification and/or mask synthesis. Typically, during the mask synthesis flow, a large number of machines are available to the user. Also, as multiple machines/cores become more ubiquitous, even designers using layout verification tools will have access to a large set of machines. Having an efficient and scalable distributed algorithm for performing sequences of layout geometry operations will be of great value to both the designer and the mask synthesis engineer.This paper seeks to present such an algorithm. Given a layout and a sequence of layout geometry operations, the layout is divided into several partitions. The given sequence of layout geometry operations is executed in parallel on the different partitions. The partitions are merged in a systematic manner and the sequence of operations is repeated on a suitable set of polygons in these newly derived partitions until a partition that covers the entire layout area is obtained. A key feature of the proposed algorithm is that it is correct-by-construction -i.e., each partition is guaranteed to generate a subset of the correct results. The complete and correct results are generated for each layout geometry operation for the entire layout when the operation completes execution on all the partitions. Results on large industrial layouts are very promising and show good performance and scalability.

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Section: Introductionmentioning

confidence: 98%

A distributed algorithm for layout geometry operations

Hsu

Sinha

et al. 2011

Proceedings of the 48th Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…The work described in this paper is part of an ongoing project called ProperCAD [15] which is aimed at developing an integrated suite of parallel applications for VLSI CAD that run on a variety of parallel platforms. In the past, various tools have been developed to solve the problems at lower levels in the VLSI CAD hierarchy, namely, placement [16], routing [17], circuit extraction [18], design rule checking [26], logic synthesis [27], [27], test generation [25], [29], fault simulation [28], and behavioral simulation [23]. In this paper,…”

Section: Introductionmentioning

confidence: 99%