Pane

Abstract

Communication between different IP cores in MPSoCs and HMPs often results in clock domain crossing. Asynchronous network on chip (NoC) support communication in such heterogeneous set-ups. While there are a large number of tools to model NoCs for synchronous systems, there is very limited tool support to model communication for multi-clock domain NoCs and analyse them. In this article, we propose the P luggable A synchronous NE twork on Chip (PANE) simulator, which allows system-level simulation of asynchronous network on chip (NoC). PANE allows design space exploration of synchronous, asynchronous, and mixed synchronous-asynchronous(heterogeneous) NoC for various system-level NoC parameters such as packet latencies, throughput, network saturation point and power analysis. PANE supports a large range of NoC configurations—routing algorithms, topologies, network sizes, and so on—for both synthetic and real traffic patterns. We demonstrate the application of PANE by using synchronous routers, asynchronous routers, and a mix of asynchronous and synchronous routers. One of the key advantages of PANE is that it allows a seamless transition from synchronous to asynchronous NoC simulators while keeping pace with the developments in synchronous NoC tools as they can be integrated with PANE.

A Multi-Agent-Based Network-on-Chip Simulator

“…It informs statistical measurements such as end-to-end latencies, throughput, and transfer latencies. The PANE simulator [15] also provides a modeling and system analysis tool for asynchronous, synchronous, and mixed synchronousasynchronous (heterogeneous), but with good improvements compared with HNOCS [14]. For example, PANE allows users to configure the NoC with delays for each functional unit.…”

“…The use of a multi-agent platform for the development of the NoC simulator demonstrate a good performance when compared to the performance of state-of-the-art high-level abstraction simulators. For instance, in [15] scenarios simi-lar to ours were used to evaluate NoCs with mesh topologies and different sizes using the PANE simulator. Test scenarios were configured with one-flit-long packets injected at 0.05 packets/router and the simulation took 235 minutes, i.e., ≈ 4 hours, to execute a 32 × 32 NoC.…”

“…By running specific scenarios, these tools help to determine channel and buffer sizing, project routing and switching techniques, assess communication performance, specify packet format, and avoid starvation caused by deadlocks. NoC simulation tools have been adopted academically and by the industry in the last years [3,4,5,6,7,8,9,10,11,12,13,14,15]. However, most of these tools present a complex interface and require extra runtime and knowledge when explored together with hardware simulation tools.…”