2013
DOI: 10.1016/j.mee.2013.04.027
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Pad roughness evolution during break-in and its abrasion due to the pad-wafer contact in oxide CMP

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Cited by 23 publications
(34 citation statements)
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“…Moreover, longer break-in times have been generally shunned since they reduce pad life, tool availability, and the overall wafer throughput in high-volume IC manufacturing environments. Several other groups of researchers have reported similar 30-min experimental conditions where a stable pad micro-texture has been achieved only after 30 min of break-in [4,7,8]. Therefore, pad break-in is performed for 5, 20 and 30 min with UPW flowing onto the centre of the rotating pad.…”
Section: Experimental Apparatus and Proceduresmentioning
confidence: 90%
“…Moreover, longer break-in times have been generally shunned since they reduce pad life, tool availability, and the overall wafer throughput in high-volume IC manufacturing environments. Several other groups of researchers have reported similar 30-min experimental conditions where a stable pad micro-texture has been achieved only after 30 min of break-in [4,7,8]. Therefore, pad break-in is performed for 5, 20 and 30 min with UPW flowing onto the centre of the rotating pad.…”
Section: Experimental Apparatus and Proceduresmentioning
confidence: 90%
“…Extensive research has shown that pad surface micro-texture plays an important role in CMP and is affected by several factors such as conditioner type, conditioning downforce, and pad break-in time [2,3,4,5,6,7,8,9,10]. In addition, laser scanning confocal microscopy has been successfully used to analyze pad surface micro-texture and has led to a better understanding of how it affects CMP performance [2,3,4,5,6,7,8,9,10]. Sun et al studied the effect of conditioner type and conditioning downforce on pad topography and found that the surface becomes more abrupt and copper removal rates decrease with increasing conditioning downforce [2].…”
Section: Introductionmentioning
confidence: 99%
“…Concurrently, however, process complexity in terms of the number of CMP steps and uniqueness of each step has also increased by orders of magnitude [1][2][3][4]. The CMP process has evolved through multiple generations, dated back to 1969 [5,6], employing a large pad and a single wafer carrier that rotated about their respective axes.…”
Section: Introductionmentioning
confidence: 99%
“…As an industrial process, CMP is expensive both in terms of capital cost, and cost of operation. Recently, with shrinking feature size (currently <15 nm), CMP has also been mired by defectivity (e.g., scratch and film delamination) [2][3][4] at a multiplicity of length-scales ranging from within wafer nonuniformity at wafer scale, within die nonuniformity at die scale to defectivity concerns at feature or nano-scale.…”
Section: Introductionmentioning
confidence: 99%