Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems 2021
DOI: 10.1145/3445814.3446724
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PacketMill: toward per-Core 100-Gbps networking

Abstract: We present PacketMill, a system for optimizing software packet processing, which (i) introduces a new model to efficiently manage packet metadata and (ii) employs code-optimization techniques to better utilize commodity hardware. PacketMill grinds the whole packet processing stack, from the high-level network function configuration file to the low-level userspace network (specifically DPDK) drivers, to mitigate inefficiencies and produce a customized binary for a given network function. Our evaluation results … Show more

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Cited by 22 publications
(13 citation statements)
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“…Applying Morpheus to a DPDK program, we increase performance by up to 469%. Finally, we measured Morpheus against state-of-the-art network code optimization frameworks such as ESwitch [62] and PacketMill [30]: we show that Morpheus boosts the throughput by up to 80% and 294%, respectively, compared to existing work. Contributions.…”
Section: Morpheusmentioning
confidence: 97%
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“…Applying Morpheus to a DPDK program, we increase performance by up to 469%. Finally, we measured Morpheus against state-of-the-art network code optimization frameworks such as ESwitch [62] and PacketMill [30]: we show that Morpheus boosts the throughput by up to 80% and 294%, respectively, compared to existing work. Contributions.…”
Section: Morpheusmentioning
confidence: 97%
“…2 The need for tracking packet-level dynamics. The potential to optimize code for specific network configurations has been explored in prior work, for OpenFlow [62], P4 software [75,86] and hardware targets [5], network functions [69], and programmable switches [30] (see Table 1). In order to maximize performance, however, we need to go beyond specializing the code for relatively stable runtime configuration and apply optimizations at the packet level.…”
Section: The Need For Dynamic Optimizationmentioning
confidence: 99%
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“…Neugebauer et al [33] have investigated the performance of the PCIe device interconnecting modern NICs to the CPUs and memories showing surprisingly low performance with small packets. Farshin et al (i) quantified the impact of direct cache access in Intel processors [9] and (ii) proposed software stack optimizations to achieve per-core hundred-gigabit networking [8]. Kuzniar et al [23,24] have unveiled a variety of issues with the initial OpenFlow-based switches, such as the lack of consistency during updates.…”
Section: Related Workmentioning
confidence: 99%