Packet Indexing Process Optimized for High-Speed Network Processors

Abstract

Most network processors perform some kind of classification on the received packet stream, according to criteria set by the implemented networking application. Packet indexing is an integral part of the packet classification process. Indexing is considered as one of the most processor intensive part of network processing and is often supported by special hardware units. High performance Network processors usually rely upon Content Addressable Memories (CAMs) for the indexing of millions of packets per second into discrete "flow Identifiers" in ATM and IP networks. Most often, the indexing process examines packet data (tags) of significant size, necessitating the use of large CAM devices. This paper proposes an alternative method for searching lengthy tags, using RAM as storage medium instead of the expensive and complex CAMs. The technique applies the open-addressing hashing methodology to provide high speed lookups, close to CAM's performance. Our approach handles efficiently the limitations imposed by the hashing algorithms by appropriately selecting system parameters and resolving hashing collisions. The advantages of the proposed method are evaluated in detail.