2011 3rd Asia Symposium on Quality Electronic Design (ASQED) 2011
DOI: 10.1109/asqed.2011.6111694
|View full text |Cite
|
Sign up to set email alerts
|

Package design optimization for efficient on-chip-capacitance leveraging

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 7 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?