P4Visor

Abstract

Programmable data planes, PDPs, enable an unprecedented level of flexibility and have emerged as a promising alternative to existing data planes. Despite the rapid development and prototyping cycles that PDPs promote, the existing PDP ecosystem lacks appropriate abstractions and algorithms to support these rapid testing and deployment life-cycles. In this paper, we propose P4Visor, a lightweight virtualization abstraction that provides testing primitives as a first-order citizen of the PDP ecosystem. P4Visor can efficiently support multiple PDP programs through a combination of compiler optimizations and program analysis-based algorithms. P4Visor's algorithm improves over state-of-the-art techniques by significantly reducing the resource overheads associated with embedding numerous versions of a PDP program into hardware. To demonstrate the efficiency and viability of P4Visor, we implemented and evaluated P4Visor on both a software switch and an FPGA-based hardware switch using fourteen different PDP programs. Our results demonstrate that P4Visor introduces minimal overheads (less than 1%) and is one order of magnitude more efficient than existing PDPs primitives for concurrently supporting multiple programs. CCS CONCEPTS • Networks → Programmable networks; • Software and its engineering → Software testing and debugging;

P4Update

“…Even though our prototype is based on a software target, we envision that with a hardware target, the processing can be accelerated with negligible overhead [59]. For the resubmission, the switch can reserve a slice with, e.g., virtualization techniques [30,77] with isolated resources to eliminate the impact on data plane processing. 2-Phase Commit Updates.…”

Poster: Continual Network Learning

“…Programming the switch at run-time is possible [32], but not for RMT [6], the common commercial devices architecture [2,13]. Researchers have also explored means to enable isolation between offloaded programs [27,30,35], which we will investigate to isolate the Active Learning processing and the rest of the pipeline.…”

Fast ReRoute on Programmable Switches

“…For instance, techniques on how to partially reconfigure an FPGA in an online manner exist [53]. Similar techniques have been explored to dynamically reconfigure the structure of the P4-based PISA forwarding tables [54], [55]. We note that an operator does not have to recompile the tables if the sequences have non-uniform lengths as long as the mapping allows to implement such sequences.…”