P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Benáček, Pavel; Pu, Viktor; Kubátová, Hana

doi:10.1109/fccm.2016.46

Cited by 41 publications

(54 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table II presents the results of the configurable packet parser experiment. In terms of throughput (omitted from the table) and latency, this work performs as well as the hand-crafted VHDL implementation reported in [41]. This work outperforms automatically generated VHDL code in all aspects except in the number of FFs.…”

Section: A Experimental Setupmentioning

confidence: 70%

“…We have conducted a different experiment where we mimic Benacek's architecture using our MpO methodology. This experiment is labelled " [41] MpO" in Table II. Architectural aspects aside, this hybrid implementation delivers better results than the original Benacek implementation, significantly reducing the latency (-10%) and the number of LUTs (-35%).…”

Section: A Experimental Setupmentioning

confidence: 99%

See 1 more Smart Citation

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

Silva

Boyer

Langlois

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

View full text Add to dashboard Cite

High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamiliar to hardware design. However, achieving the highest Quality-of-Results (QoR) with HLS is still unattainable for most programmers. This requires detailed knowledge of FPGA architecture and hardware design in order to produce FPGA-friendly codes. Moreover, these codes are normally in conflict with best coding practices, which favor code reuse, modularity, and conciseness.To overcome these limitations, we propose Module-per-Object (MpO), a human-driven HLS design methodology intended for both hardware designers and software developers with limited FPGA expertise. MpO exploits modern C++ to raise the abstraction level while improving QoR, code readability and modularity. To guide HLS designers, we present the five characteristics of MpO classes. Each characteristic exploits the power of HLS-supported modern C++ features to build C++based hardware modules. These characteristics lead to highquality software descriptions and efficient hardware generation. We also present a use case of MpO, where we use C++ as the intermediate language for FPGA-targeted code generation from P4, a packet processing domain specific language. The MpO methodology is evaluated using three design experiments: a packet parser, a flow-based traffic manager, and a digital upconverter. Based on experiments, we show that MpO can be comparable to hand-written VHDL code while keeping a high abstraction level, human-readable coding style and modularity. Compared to traditional C-based HLS design, MpO leads to more efficient circuit generation, both in terms of performance and resource utilization. Also, the MpO approach notably improves software quality, augmenting parameterization while eliminating the incidence of code duplication.

show abstract

Section: A Experimental Setupmentioning

confidence: 70%

Section: A Experimental Setupmentioning

confidence: 99%

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

Silva

Boyer

Langlois

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

View full text Add to dashboard Cite

show abstract

“…The target FPGA device of this work was a Xilinx Virtex-7 FPGA. Table 1 shows a comparison against others works present in the literature [2,6] that support fixed-and variable-sized headers.…”

Section: Resultsmentioning

confidence: 99%

“…To compare the impact of our proposed pipelined layout, we implemented the pipeline organization proposed in [2] using the proposed header block architecture illustrated in Figure 1b since their source code was unavailable. This experiment is marked as "Hybrid [2] and this work" in Table 1. For the simple parser, our proposed architecture improves latency by more than 33%, while reducing by 16% and 10% number of used FFs and LUTs, respectively.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

Silva

Boyer

Langlois

2018

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN networks need to be both reconfigurable and fast, to support the evolving network protocols and the increasing multi-gigabit data rates. The combination of packet processing languages with FPGAs seems to be the perfect match for these requirements.In this work, we develop an open-source FPGA-based configurable architecture for arbitrary packet parsing to be used in SDN networks. We generate low latency and high-speed streaming packet parsers directly from a packet processing program. Our architecture is pipelined and entirely modeled using templated C++ classes. The pipeline layout is derived from a parser graph that corresponds a P4 code after a series of graph transformation rounds. The RTL code is generated from the C++ description using Xilinx Vivado HLS and synthesized with Xilinx Vivado. Our architecture achieves 100 Gb/s data rate in a Xilinx Virtex-7 FPGA while reducing the latency by 45% and the LUT usage by 40% compared to the state-of-the-art.

show abstract

A Bufferless Non-exact Matching Hardware Accelerator for Processing Large Non-uniform Stream Data

Duong

Trinh

et al. 2021

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

View full text Add to dashboard Cite

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Cited by 41 publications

References 6 publications

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs

A Bufferless Non-exact Matching Hardware Accelerator for Processing Large Non-uniform Stream Data

Contact Info

Product

Resources

About