P-N double quantum well resonant interband tunneling diode with peak-to-valley current ratio of 144 at room temperature

Tsai, Hann Huei; Su, Y. K.; Lin, Huang-Hsuan; Wang, R.L.; Lee, T.L.

doi:10.1109/55.311133

Cited by 51 publications

(17 citation statements)

References 14 publications

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“…5; for a given device, small fluctuations ($1% in voltage peak position and $6% in peak current) are observed with consecutive positive and negative sweeps but could be attributed to temperature fluctuations of $2 K (within the experimental thermal stability). The performance exceeds that observed in typical solid state quantum well resonant tunneling heterostructures [26][27][28][29]. In addition to the obvious size advantages for scaling, the intrinsic device characteristics (that is, the valley current shutoff) may be superior to that of solid state devices.…”

Section: Ndr In Molecular Junctionsmentioning

confidence: 74%

Electronic transport of molecular systems

2002

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We report stable and reproducible switching and memory effects in self-assembled monolayers (SAMs). We demonstrate realization of negative differential resistance (NDR) and charge storage in electronic devices that utilize single redox-center-contained SAM as the active component; and compare the effects of various redox centers to switching and storage behavior. The devices exhibit electronically programmable and erasable memory bits with bit retention times greater than 15 min at room temperature. Ó

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Section: Ndr In Molecular Junctionsmentioning

confidence: 74%

Electronic transport of molecular systems

2002

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“…In terms of the above-mentioned figures-of-merit, the main differences between Si-and III-V-based diodes lie in the inherent higher PVCR obtained in the III-V semiconductor structures. Even though an absolute maximum ratio of 144 has been reported [12] for III-V-based materials, values in the range of 30-50 are more typical for III-V interband semiconductor structures [4]. On the other hand, silicon devices hardly reach the value of four for interband structures and even worse for the intraband TDs.…”

Section: A Semiconductor Structuresmentioning

confidence: 94%

“…Once these current components are determined, the linear conversion matrix analysis can be used to find the voltage across and the current in the embedding impedance at the IM3 frequency. The third-order current in is (12) where is the diagonal matrix of the embedding impedance at the third-order mixing frequency. The power dissipated in the embedding impedance at the IM3 component is (13) The power content at IM3 depends upon the characteristics of the diode.…”

Section: A Hitd-based Mixermentioning

confidence: 99%

MMIC applications of heterostructure interband tunnel devices

Cidronali

Nair

Collodi

et al. 2003

IEEE Trans. Microwave Theory Techn.

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This paper deals with recent achievements in the field of an emerging technology termed the quantum monolithic microwave integrated circuit (QMMIC). QMMIC consists of a heterojunction interband tunneling diode and a high electron-mobility transistor monolithically integrated to obtain a new functional device. This technology enables the realization of low-voltage, high-density, and high-functionality circuits. A detailed description of the design and analysis techniques for several circuits such as an amplifier, an oscillator, and a mixer, along with the analytical treatment of the principle of operation are given in this paper. A number of prototypes implemented in InP technology constitute the proof-of-concept of the unique features of QMMIC circuit blocks for low-power wireless systems.Index Terms-Linear mixer, low power, monolithic microwave integrated circuit (MMIC), quantum-well devices, RF identification (RF ID), voltage-controlled oscillator (VCO).

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“…Fig. 22(b) illustrates the power consumption for a PVCR of 144 (The highest PVCR reported for any NDR device [29]). An order of magnitude reduction in standby power is observed (standby 7 nW).…”

Section: Power Analysismentioning

confidence: 98%

90 nm 32 $\times$ 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

Anisha

Park

Berger

2011

IEEE Trans. Circuits Syst. I

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Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T-2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic "1" and 0 V as a logic "0". Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6 10 5 mW per cell and dynamic power dissipation of 1 8 10 7 mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.Index Terms-Embedded memory, low power memory, negative differential resistance (NDR), resonant interband tunnel diodes, tunnel diodes, tunnel static random access memory (SRAM).

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P-N double quantum well resonant interband tunneling diode with peak-to-valley current ratio of 144 at room temperature

Cited by 51 publications

References 14 publications

Electronic transport of molecular systems

Electronic transport of molecular systems

MMIC applications of heterostructure interband tunnel devices

90 nm 32 $\times$ 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

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