P‐6.16: Design of Hardware Accelerator for Real‐Time Edge Detection System Based on FPGA

Abstract

Edge detection is an important research field in image processing and computer vision, especially in feature extraction. The detection efficiency of the traditional Sobel edge detection algorithm is reduced due to serial instructions, and its recognition ability for complex image textures is weak. The threshold needs to be set artificially. In this context, we present an improved Sobel algorithm, which enlarges the traditional operator convolution factor size to 5×5, extends the direction to 16 directions, and introduces the median as a local adaptive threshold for judgment. The improved algorithm is implemented using FPGA and MATLAB respectively, and processes image data with a resolution of 1280×720. The experimental results show that: When the clock frequency of the image processing module is 84 MHz, the FPGA processes a 1280×720 image in about 0.0109 s, while the MATLAB processes the same image in an average time of 0.915 s. The Sobel edge detection algorithm proposed in this work effectively denoises the image while also detecting the edge information of the image efficiently and accurately. The algorithm processing speed is improved by about 84 times, which can well meet the real‐time requirements of video image processing systems.